A processor architecture includes a register file hierarchy to implement virtual registers that provide a larger set of registers than those directly supported by an instruction set architecture to facilitate multiple copies of the same architecture register for different processing threads, where the register file hierarchy includes a plurality of hierarchy levels. The processor architecture further includes a plurality of execution units coupled to the register file hierarchy.

In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

A data processing apparatus comprises receiver circuitry for receiving instructions from each of a plurality of requester devices. Processing circuitry executes the instructions associated with each of a subset of the requester devices at a time and arbitration circuitry determines the subset of the requester devices and causes the instructions associated with each of the subset of the requester devices to be executed next. In response to the receiver circuitry receiving an instruction of a predetermined type from one of the requester devices outside the subset of requester devices, the arbitration circuitry causes the instruction of the predetermined type to be executed next.

A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.

Operand liveness state information is maintained during context switches for current architected operands of executing programs. The current operand state information indicates whether corresponding current operands are enabled or disabled for use by a first program module comprising machine instructions of an instruction set architecture (ISA) for disabling current architected operands. A machine instruction of the first program module accesses a current operand by using the current operand state information to determine whether a previously stored current operand value is accessible by the first program module.

An approach is provided in which a mapper control unit receives dispatch information corresponding to an instruction that targets a first field in a first register and a second field in a second register, the first register being a first register type and the second register being a second register type. As such, the mapper control unit selects a history buffer entry in a history buffer that is adapted to concurrently store content corresponding to the first register type and the second register type. In turn, the mapper control unit stores first content from the first register's targeted first fields and second content from the second register's targeted second fields into the selected history buffer entry.

Operand liveness state information is maintained during context switches for current architected operands of executing programs. The current operand state information indicates whether corresponding current operands are enabled or disabled for use by a first program module comprising machine instructions of an instruction set architecture (ISA) for disabling current architected operands. A machine instruction of the first program module accesses a current operand by using the current operand state information to determine whether a previously stored current operand value is accessible by the first program module.

The invention provides multiple secure virtualized environments operating in parallel with optimal resource usage, power consumption and performance. The invention provides a method whereby virtual machines (VMs) have direct access to the computing system's hardware without adding traditional virtualization layers while the hypervisor maintains hardware-enforced isolation between VMs, preventing risks of cross-contamination. Additionally, some of the VMs can be deactivated and reactivated dynamically when needed, which saves the computing system resources. As a result, the invention provides bare-metal hypervisor use and security but without the limitations that make such hypervisors impractical, inefficient and inconvenient for use in mobile devices due to the device's limited CPU and battery power capacity.

A method for populating an instruction view data structure by using register template snapshots. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions; populating and instruction view data structure, wherein the instruction view data structure stores instructions corresponding to the instruction blocks as recorded by the plurality of register templates; and using the instruction view data structure to feed a plurality of stacked execution units of execution stage in accordance with the readiness of instruction sources of the instruction blocks.

An apparatus and method are provided for controlling instruction execution behaviour. The apparatus includes a set of data registers for storing data values, and a set of bounded pointer storage elements, where each bounded pointer storage element stores a pointer having associated range information indicative of an allowable range of addresses when using that pointer. A control storage element stores a current instruction context, and that current instruction context is used to influence the behaviour of at least one instruction executed by processing circuitry, that at least one instruction specifying a pointer reference for a required pointer, where the pointer reference is within at least a first subset of values (in one embodiment the behaviour is influenced irrespective of the value of the required pointer). In particular, when the current instruction context identifies a default state, the processing circuitry uses the pointer reference to identify one of the data registers whose stored data value forms the required pointer. However, when the current instruction context identifies a bounded pointer state, the processing circuitry instead uses the pointer reference to identify one of the bounded pointer storage elements whose stored pointer forms the required pointer. This allows an instruction set to be provided that can be used for both bounded pointer aware code and bounded pointer unaware code, without significantly increasing the pressure on instruction set encoding space.