The invention provides multiple secure virtualized environments operating in parallel with optimal resource usage, power consumption and performance. The invention provides a method whereby virtual machines (VMs) have direct access to the computing system's hardware without adding traditional virtualization layers while the hypervisor maintains hardware-enforced isolation between VMs, preventing risks of cross-contamination. Additionally, some of the VMs can be deactivated and reactivated dynamically when needed, which saves the computing system resources. As a result, the invention provides bare-metal hypervisor use and security but without the limitations that make such hypervisors impractical, inefficient and inconvenient for use in mobile devices due to the device's limited CPU and battery power capacity.

Context switch by changing memory pointers. A determination is made that a context switch is to be performed from a first context to a second context. Data of the first context is stored in one or more configuration state registers stored at least in part in a first memory unit and data of the second context is stored in one or more configuration state registers stored at least in part in a second memory unit. The context switch is performed by changing a pointer from the first memory unit to the second memory unit.

The various embodiments of the present invention disclose a method for reducing interrupt latency in embedded systems. According to at least one example embodiment of the inventive concepts, the method for reducing interrupt latency in embedded systems, the method comprises steps of toggling, by a processor, from a supervisor (SVC) mode to an interrupt request (IRQ) mode on receiving an interrupt, identifying, by the processor, a Task Control Block (TCB) of a preempted task on receiving the interrupt, enabling, by the processor, the IRQ stack as a pseudo preempted task context table, and storing the preempted task context information in the IRQ stack, wherein a register set is stored in IRQ stack before processing the received interrupt.

A processing apparatus comprising one or more processing modules, each comprising an execution unit. The one or more processing modules are operable to run a plurality of parallel or concurrent threads, and the processing apparatus further comprises a storage location for storing an aggregated exit state of the plurality of threads. An instruction set of the processing apparatus comprises an exit instruction for inclusion in each of the plurality of threads, the exit state instruction taking an individual exit state of the respective thread as an operand. The exit instruction terminates the respective thread and also causes the individual exit state specified in the operand to contribute to the aggregated exit state.

A method, computer system, and a computer program product for designing and executing at least one storlet is provided. The present invention may include receiving a plurality of restore operations based on a plurality of data. The present invention may also include identifying a plurality of blocks corresponding to the received plurality of restore operations from the plurality of data. The present invention may then include identifying a plurality of grain packs corresponding with the identified plurality of blocks. The present invention may further include generating a plurality of grain pack index identifications corresponding with the identified plurality of grain packs. The present invention may also include generating at least one storlet based on the generated plurality of grain pack index identifications. The present invention may then include returning a plurality of consolidated objects by executing the generated storlet.

A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.

A processor comprising: an execution unit, multiple context register sets, a scheduler arranged to control the execution unit to provide a repeating sequence of temporally interleaved time slots, thereby enabling at least one respective worker thread to be allocated for execution in each respective one of some or all of the time slots, wherein a program state of the respective worker thread currently executing in each time slot is maintained in a respective one of the context register sets; and an exit state register arranged to store an aggregated exit state the worker threads. The instruction set comprises an exit instruction for inclusion in each worker thread, the exit state instruction taking an individual exit state of the respective thread as an operand. The exit instruction terminates the respective worker and also cause the individual exit state specified in the operand to contribute to the aggregated exit state.

A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a plurality of execution units to process graphics context data and a register file having a plurality of registers to store the graphics context data; and register renaming logic to facilitate re-use of register data by partitioning a first part and a second part, the first part to include thread-independent code and the second part to include thread-dependent code.

Disclosed herein is an apparatus which comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units.

A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.