A Qround process is executed in a Round process for respective blocks related to the ChaCha algorithm. At that time, in a case where a target round to be operated is a specific round, the execution of the Qround process is skipped. Accordingly, unnecessary process steps are eliminated in execution of the ChaCha algorithm.

Systems and methods are provided for the deterministic simulation of distributed systems, such as vehicle-based processing systems. A distributed system may be represented as a plurality of subsystems or nodelets executing with a single process of a computing device during a simulation. The nodelets may communicate using in-process communication. A task scheduler can schedule the nodelets to execute separately in serially-occurring frames. A simulated clock may be used to mitigate the variability in timestamped data that may be caused by latency or jitter.

Techniques are disclosed relating to task execution with non-blocking calls. A computer system may receive a request to perform an operation comprising a plurality of tasks, each of which corresponds to a node in a graph. A particular one of the plurality of tasks specifies a call to a downstream service. The computer system may maintain a plurality of task queues, each of which is associated with a thread pool. The computer system may enqueue, in an order specified by the graph, the plurality of tasks in one or more of the plurality of task queues. The computer system may process the plurality of tasks. Such processing may include a thread of a particular queue in which the particular task is enqueued performing a non-blocking call to the downstream service. After processing the plurality of tasks, the computer system may return a result of performing the operation.

A method and apparatus are disclosed for a multi-processor system on a chip which includes at least a first execution domain processor that is configured to run a first execution domain by accessing one or more system-on-chip resources; a first control point processor that is physically and programmatically independent from the first execution domain processor and that is configured to generate a first runtime isolation control data stream for controlling access to the one or more system-on-chip resources by the first execution domain; and an access control circuit connected between the first execution domain processor and the one or more system-on-chip resources and configured to provide a dynamic runtime isolation barrier in response to the first runtime isolation control data stream, thereby controlling access to the one or more system-on-chip resources by the first execution domain.

A technique for generating component usage statistics involves associating components with blocks of a stream-enabled application. When the streaming application is executed, block requests may be logged by Block ID in a log. The frequency of component use may be estimated by analyzing the block request log with the block associations.

A partial order procedure planning device 10 is provided with: a first generation unit 11 which generates a first condition of a removable order relationship under a predetermined restriction among order relationships between operations in a serial procedure in which a plurality of operations, which transit the state of a state element from an initial state to a target state, are arranged in series; a second generation unit 12 which generates a second condition of an order relationship, which is required to satisfy a transient requirement that is required to satisfy the state element while a state among the order relationships is transitioned from the initial state to the target state; and a determination unit 13 which determines, as the order relationship to be deleted from the serial procedure, an order relationship which satisfies the generated first condition, but does not satisfy the generated second condition.

Embodiments of the present disclosure disclose an artificial intelligence chip and an instruction execution method for an artificial intelligence chip. A specific embodiment of the artificial intelligence chip includes: an instruction memory, a data memory, at least one general execution unit, and at least one dedicated execution unit. The instruction memory is configured to: receive a kernel code including at least one code block. The general execution unit is configured to: receive the code block, lock the dedicated execution unit associated with the received code block, and send an instruction in the received code block to the locked dedicated execution unit. The dedicated execution unit is configured to: execute the received instruction, and store an execution result in the data memory. The data memory is configured to: store the execution result sent by the dedicated execution unit.

The exemplary embodiments are related to a pipeline manager configured to manage a software development pipeline. The pipeline manager receives, via a user interface (UI), a representation of a pipeline comprising a plurality of blocks, wherein each block comprises a defined input and a defined output, executes each block of the pipeline, validates output of each block of the pipeline based on the execution of the block and stores the output of each block and updating data that defines the pipeline based on the output of each block.

A computer-implemented method includes creating a first file control block in a primary runtime environment with a first addressing mode and a second file control block in a secondary runtime environment with a second addressing mode, where both the first file control block and the second file control block describe a status of a first file of a caller program in the primary runtime environment. The parameters of the first file of the caller program in the primary runtime environment are passed to a target callee program in the secondary runtime environment. An anchor is added in the first file control block as a link to the second file control block. The first file control block are the second file control block synchronized with updates to the first file in the primary runtime environment and the passed parameters of the first file in the secondary runtime environment.

The various embodiments of the present invention disclose a method for reducing interrupt latency in embedded systems. According to at least one example embodiment of the inventive concepts, the method for reducing interrupt latency in embedded systems, the method comprises steps of toggling, by a processor, from a supervisor (SVC) mode to an interrupt request (IRQ) mode on receiving an interrupt, identifying, by the processor, a Task Control Block (TCB) of a preempted task on receiving the interrupt, enabling, by the processor, the IRQ stack as a pseudo preempted task context table, and storing the preempted task context information in the IRQ stack, wherein a register set is stored in IRQ stack before processing the received interrupt.