A method of requesting data items from storage. The method comprising allocating each of a plurality of memory controllers a unique identifier and assigning memory transaction requests for accessing data items to a memory controller according to the unique identifiers. The data items are spatially local to one another in storage. The data items are requested from the storage via the memory controllers according to the memory transaction requests and then buffered if the data items are received out of order relative to an order in which the data items are requested.

Various multi-processor unified memory management systems and methods are detailed herein. In embodiments detailed herein, inter-chip memory management modules may be executed by processors that are in communication via an inter-chip link. A flat memory map may be used across the multiple processors of the system. Each inter-chip memory management module may analyze memory transactions. If the memory transaction is directed to a portion of the flat memory map managed by another processor, the memory-transaction may be translated to a non-memory mapped transaction and transmitted via an inter-chip communication link.

A method, computer program product, and computer system for receiving an XCopy command is provided. The XCopy command may be in the form of an IO operation. The IO operation may be a subextent block operation. A source range and a destination range of the XCopy command may be determined to be aligned within an alignment boundary. The Xcopy command may be determined to be smaller than a predetermined size. In response to determining the source range and destination range of the XCopy command are aligned within the alignment boundary and the XCopy command is smaller than a predetermined size, the XCopy command may be processed. The receiving of the XCopy command may be recorded in a log.

A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a transaction pipeline and a pool of counters. The I/O agent circuit may initialize a first counter included in the pool of counters with an initial counter value. The I/O agent circuit may assign the first counter to a specific transaction type. The I/O agent circuit may increment the first counter as a part of allocating a transaction of a transaction type included in a set of transaction types different than the specific transaction type. Based on receiving a transaction request to process a first transaction of the specific transaction type, the I/O agent circuit may bind the first transaction to the first counter. The I/O agent circuit may issue the first transaction to the transaction pipeline based on a counter value stored by the first counter matching the initial counter value.

A data processing apparatus has processing circuitry with transactional memory support circuitry to support execution of a transaction using transactional memory. In response to an exception mask updating instruction which updates exception mask information to enable at least one subset of exceptions which was disabled at the start of processing of a transaction, the processing circuitry permits un-aborted processing of one or more subsequent instruction of the transaction that follow the exception mask update instruction.

A method includes receiving, by a MMU for a processor core, an address translation request from the processor core and providing the address translation request to a TLB of the MMU; generating, by matching logic of the TLB, an address transaction that indicates whether a virtual address specified by the address translation request hits the TLB; providing the address transaction to a general purpose transaction buffer; and receiving, by the MMU, an address invalidation request from the processor core and providing the address invalidation request to the TLB. The method also includes, responsive to a virtual address specified by the address invalidation request hitting the TLB, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.

Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.

A memory controller with a separate transaction table for real-time transactions is disclosed. A system includes a plurality of agents and a memory controller configured to receive real-time and non-real-time memory requests from ones of the plurality of agents. The memory controller includes a real-time incoming transaction table configured to store those memory requests received from a subset of the plurality of agents that are real-time memory requests, and a non-real-time incoming transaction table configured to store those memory requests received from the subset of the plurality of agents that are non-real-time memory requests. The memory controller further includes an arbitration circuit configured to select a memory request from among memory requests stored in the real-time and non-real-time incoming transaction tables and further configured to enforce a quality of service policy for the real-time memory requests.

Systems and methods for regulating memory utilization for coprocessors are provided. In one embodiment, a computing system comprises: a processor; a compute processor configured to execute one or more kernels; a memory coupled to the processor and the compute processor. The system is configured to: allocate at least one task memory transaction quota to at least a first set of tasks executed on a first core of the processor; allocate at least one compute processor memory transaction quota for executing the kernels on the compute processor; execute within a first timing window iteration the first set of tasks and the kernels, wherein the kernels are executed during the first timing window iteration until the compute memory transaction quota is depleted; and regulate a rate of memory transaction access by the one or more kernels to the memory when the first set of tasks are executing on the processor.