A method, computer program product, and computing system for receiving a plurality of lock sequences associated with a plurality of objects of the computing device. A plurality of matrices may be generated for each lock sequence of the plurality of lock sequences, thus defining a plurality of lock sequence matrix towers. The plurality of lock sequence matrix towers may be combined, thus defining a combined lock sequence matrix tower. One or more lock sequence conflicts may be identified within the plurality of lock sequences based upon, at least in part, the combined lock sequence matrix tower.

Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and transition logic configured to cause the processor to transition to a safe state when livelock has been detected by the detection logic.

A computer-implemented method includes the following operations. A transactional lock elision transaction including a critical section is executed. The critical section is processed. After the processing of the critical section and prior to a commit point in the transactional lock elision transaction, a status of a lock is checked. Responsive to a determination that a status of the lock is free, a result of the transactional lock elision transaction is committed.

To be capable of concurrent execution of a function group not in data conflict by a plurality of cores and to execute a function pair in data conflict in a temporal separation manner. A process barrier 20 includes N−1 checker functions 22 and one limiter function 23, where the number of cores capable of concurrently executing the functions is N (N is an integer equal to or greater than 2), the checker functions 22 determine whether the head entry of a lock-free function queue LFQ1 is either the checker function 22 or the limiter function 23, and repeats reading of the head entry of the lock-free function queue LFQ1 if either, and ends processing if neither, and the limiter function 23 is an empty function ending without performing any processing.

Systems and methods are directed to methods and apparatus for transferring ownership of common resources from a source entity, which owns a resource, to a destination entity, which will own the resource, in a distributed system. The method includes the source entity receiving a command to change ownership (the MOVE command), and then marking the source entity as no longer owning the common resource. The source entity then sends a MOVE command to the destination entity, which will then update its common resource ownership table to reflect that the ownership of the common resource has been transferred from the source entity to the destination entity. It is advantageous that the updating of ownership of the common resource in the source entity occur simultaneously with the dispatching of the MOVE command to the destination entity.

Parallel processors typically allocate resources to workloads based on workload priority. Priority inversion of resource allocation between workloads of different priorities reduces the operating efficiency of a parallel processor in some cases. A parallel processor mitigates priority inversion by soft-locking resources to prevent their allocation for the processing of lower priority workloads. Soft-locking is enabled responsive to a soft-lock condition, such as one or more priority inversion heuristics exceeding corresponding thresholds or multiple failed allocations of higher priority workloads within a time period. In some cases, priority inversion heuristics include quantities of higher priority workloads and lower priority workloads that are in-flight or incoming, ratios between such quantities, quantities of render targets, or a combination of these. The soft-lock is released responsive to expiry of a soft-lock timer or incoming or in-flight higher priority workloads falling below a threshold, for example.

Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and transition logic configured to cause the processor to transition to a safe state when livelock has been detected by the detection logic.

A method is provided for detecting a race condition of a parallel task when accessing a shared resource in a multi-core processing system. The method requires that a core requires only a read access to the data set of another core, thereby ensuring better decoupling of the tasks. In an initialisation phase, initial values of global variables are assigned, in an activation phase, each core determines if the other core has written new values to the variables and if so, detects a race condition. Initial values are restored for each variable in a deactivation phase.

Apparatuses, methods and storage medium associated with spinlock are disclosed herein. In embodiments, an apparatus for computing may comprise a first and a second processor core to correspondingly execute a first and a second thread; a storage location to store a spinlock to facilitate exclusive access by the first or the second thread to a plurality of resources implicitly shared by the first and second threads; and spin logic to be executed by the second processor core to occupy the second processor core to suspend execution of the second thread to prevent the second thread from using any one of the implicitly shared resources, whenever the spinlock is set by the first thread for exclusive access to one or more of the implicitly shared resources. Other embodiments may be disclosed or claimed.

Embodiments relate to managing exclusive control of a shareable resource between a plurality of concurrently executing threads. An aspect includes determining the number of concurrently executing threads waiting for exclusive control of the shareable resource. Another aspect includes, responsive to a determination that the number of concurrently executing threads waiting for exclusive control of the shareable resource exceeds a pre-determined value, one or more of said concurrently executing threads terminating its wait for exclusive control of the shareable resource. Another aspect includes, responsive to a determination that the number of concurrently executing threads waiting for exclusive control of the shareable resource is less than a pre-determined value, one or more of said one or more concurrently executing threads which terminated its wait for exclusive control of the shareable resource, restarting a wait for exclusive control of the shareable resource.