A multi-thread synchronization method includes that a first thread requests to obtain a target lock. Then, the first thread checks the lock thread identifier field. The first thread checks the blocked thread quantity field when checking that the lock thread identifier field is a valid thread and is not the first thread. The first thread performs spin wait when checking that the blocked thread quantity field is less than a first threshold. When a quantity of times for spin wait reaches a second threshold and when it is checked that the lock thread identifier field is the valid thread and is not the first thread, the first thread performs an operation of adding 1 to the blocked thread quantity field, and suspends to enter a blocked state.

Methods of arbitrating between requestors and a shared resource are described. The method comprises generating a vector with one bit per requestor, each initially set to one. Based on a plurality of select signals (one per decision node in a first layer of a binary decision tree, where each select signal is configured to be used by the corresponding decision node to select one of two child nodes), bits in the vector corresponding to non-selected requestors are set to zero. The method is repeated for each subsequent layer in the binary decision tree, based on the select signals for the decision nodes in those layers. The resulting vector is a priority vector in which only a single bit has a value of one. Access to the shared resource is granted, for a current processing cycle, to the requestor corresponding to the bit having a value of one.

The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors and an inter-processor communication (IPC) unit. The IPC unit includes one or more doorbell registers, wherein each doorbell register is associated with a uniquely assigned source processor and a uniquely assigned target processor. Each doorbell register is further configured to store doorbell data indicative of whether an interrupt is a high priority interrupt or a low priority interrupt. The IPC unit may also include one or more FIFO (first-in first-out) memories configured to store data associated with each interrupt.

A method for resource exclusion, a terminal device, and a storage medium are disclosed in the present disclosure. The method includes the following. Obtain a first candidate resource set by performing a first resource exclusion operation on a first resource set in a resource selection window, where the first resource set includes available resources in a resource pool used by the terminal device in the resource selection window, the first resource exclusion operation includes performing resource exclusion according to a non-sensing slot in a resource sensing window, and the non-sensing slot represents a slot in which the terminal device performs no sensing. Determine a second resource set on condition that a first percentage is smaller than X %, where the first percentage is a percentage of number of resources in the first candidate resource set and number M.sub.total of resources in the first resource set.

A first workload is executed in a first subset of pipelines of a processing unit. A second workload is executed in a second subset of the pipelines of the processing unit. The second workload is dependent upon the first workload. The first and second workloads are suspended and state information for the first and second workloads is stored in a first memory in response to suspending the first and second workloads. In some cases, a third workload executes in a third subset of the pipelines of the processing unit concurrently with executing the first and second workloads. In some cases, a fourth workload is executed in the first and second pipelines after suspending the first and second workloads. The first and second pipelines are resumed on the basis of the stored state information in response to completion or suspension of the fourth workload.

Embodiments relate to a system, program product, and method for implementing loop lock reservations, and, more specifically, for holding a lock reservation across some or all of the iterations of a loop, and under certain conditions, temporarily effect a running thread to yield the reservation and allow other threads to enter the lock.

A method, computer program product, and computer system for permitting, by a computing device, entering of a barrier object of a plurality of barrier objects with a first set of one or more Application Programming Interfaces (APIs) only when the barrier object is not set. The first set of the one or more APIs on the barrier object may wait until the barrier object is reset. A second set of the one or more APIs may set the barrier object. Waiting may occur until there are no longer any flows in the barrier object.

Methods, systems, and devices for access control configurations for inter-processor communications are described to support reconfiguration of a dynamic access control configuration at a device. For example, additional configuration fields may be added to existing access control rules of the device, where these additional fields may be configured by a processor sending information to a receiving processor, via a shared memory resource or region of the device. The additional fields may include a read-only value which may specify a processor which has exclusive write permission for a memory region of the share memory. This value may indicate the sending processor of the memory region, and the value may be set by access control hardware when the additional field is changed. Other processors of the device may be prevented from writing to the memory region.

Techniques for executing an atomic command in a distributed computing network are provided. A core cluster, including a plurality of processing cores that do not natively issue atomic commands to the distributed computing network, is coupled to a translation unit. To issue an atomic command, a core requests a location in the translation unit to write an opcode and operands for the atomic command. The translation unit identifies a location (a “window”) that is not in use by another atomic command and indicates the location to the processing core. The processing core writes the opcode and operands into the window and indicates to the translation unit that the atomic command is ready. The translation generates an atomic command and issues the command to the distributed computing network for execution. After execution, the distributed computing network provides a response to the translation unit, which provides that response to the core.

A memory controller circuit is disclosed which is coupleable to a first memory circuit, such as DRAM, and includes: a first memory control circuit to read from or write to the first memory circuit; a second memory circuit, such as SRAM; a second memory control circuit adapted to read from the second memory circuit in response to a read request when the requested data is stored in the second memory circuit, and otherwise to transfer the read request to the first memory control circuit; predetermined atomic operations circuitry; and programmable atomic operations circuitry adapted to perform at least one programmable atomic operation. The second memory control circuit also transfers a received programmable atomic operation request to the programmable atomic operations circuitry and sets a hazard bit for a cache line of the second memory circuit.