Systems and methods for providing inter-process communication in a wearable computing device are disclosed. A hardware abstraction layer is provided for a plurality of physical devices. An application program accesses the plurality of physical devices via the hardware abstraction layer. A unique inter-process communication context is created for each application program and physical device pair. A socket interface is provided for each unique inter-process communication context.

An image signal processor, comprising an input module for obtaining input data from a camera, whereby the camera is arranged to capture a representation of a real-world environment. The image signal processor further comprises at least one adjustment module for compressing the input data and producing compressed input data, and a localization and mapping module arranged to generate one or more data points from the compressed input data. The image signal processor also comprises an output module for outputting at least the one or more data points.

A neural network operation apparatus includes: a buffer configured to store data for a neural network operation; a processor configured to change a fetching order of the data based on an observation range for fetching the data and a size of the buffer; and a first multiplexer configured to multiplex at least a portion of the data having the changed fetching order.

Techniques are provided for high availability events in a layered architecture. In an example two computing nodes coordinate to provide a computing service, where each node has a base operating system configured to fence the other base operating system, and an application configured to fence the other application. In some examples, fencing requests by an application are routed through its base operating system, which coordinates application-level fencing requests and operating system-level fencing requests.

Methods and systems include processors and hardware accelerators. The processor initiates a first process in a first hardware accelerator configured to aid the processor in performing the first process. The processor initiates the first process using one or more interface registers. The processor performs additional processing while the first hardware accelerator performs the first process after initiation of the first process. The processor also initiates a second process in a second hardware accelerator configured to aid the processor in performing a second process. Moreover, the processor initiates the second process using the one or more interface registers.

Orchestrating data pipelines in a pre-orchestrated manner. In some instances, workflows and microservices are performed in stages. The order in which these stages are performed are pre-dominantly non-sequential in order to ensure that the most relevant stages are performed in a manner that allows the workflows to be processed and microservices to be utilized in the most efficient manner possible. In some instances, when the processes in the first stage is complete, a broadcast message is published to a topic that indicates that the first stage is completed and the second stage can commence. In order to determine which processes can be performed in the second stage, a configuration table is utilized. This general process is repeated until each stage in the data pipeline is complete.

The described technology relates to a publish-subscribe message framework in which an application, decomposed to a plurality of processing stages, is run by executing respective processing stages of the application asynchronously and simultaneously with each other. Communications between the respective processing stages may exclusively be in accordance with the publish-subscribe execution model. The described publish-subscribe framework provides for processing stages to be executed in a multi-process and/or multi-threaded manner while also enabling the distribution of the processing stages to respective processing resources in a multi-processor/multi-core processing environment. An example electronic exchange application and a corresponding example exchange gateway application are described.

A method and apparatus of a network device that allocates a shared memory buffer for an object is described. In an exemplary embodiment, the network device receives an allocation request for the shared memory buffer for the object. In addition, the network device allocates the shared memory buffer from shared memory of a network device, where the shared memory buffer is accessible by a writer and a plurality of readers. The network device further returns a writer pointer to the writer, where the writer pointer references a base address of the shared memory buffer. Furthermore, the network device stores the object in the shared memory buffer, wherein the writer accesses the shared memory using the writer pointer. The network device further shares the writer pointer with at least a first reader of the plurality of readers. The network device additionally translates the base address of the shared memory buffer to a reader pointer, where the reader pointer is expressed in a memory space of the first reader.

A client device sends a connection request to a virtual system in a Kubernetes cluster. The connection request identifies the client device and the application to which the request pertains. Based on a tenant associated with the client device, the virtual system connects the client device to an instance of the application. The instance of the application has access to data for the tenant but not for other tenants. Another client device of the tenant sends another connection request to the virtual system for a connection to another application. Because the tenant is the same, the instance of the other application may access the same data as the instance of the first application. In this way, applications for a single tenant may share data while maintaining the security of the data from other tenants.

A system includes a memory including a ring buffer having a plurality of slots, a processor in communication with the memory, a guest operating system, and a hypervisor. The hypervisor is configured to detect a request associated with a memory entry, retrieve up to a predetermined quantity of memory entries in the ring buffer from an original slot to an end slot, and test a respective descriptor of each successive slot from the original slot through the end slot while the respective descriptor of each successive slot in the ring buffer remains unchanged. Additionally, the hypervisor is configured to execute the request associated with the memory entries and respective valid descriptors. The hypervisor is also configured to walk the ring buffer backwards from the end slot to the original slot while clearing the valid descriptors.