Technologies are described for restarting an application while maintaining data in memory (e.g., using shared memory). For example, shared memory can be associated with an application. The shared memory can also be associated with a holder process to maintain the shared memory from the time the application stops to the time the application starts again. When the application starts, the shared memory can be associated with the started application. In addition, restart of in-memory databases can be provided using shared memory. For example, in-memory data can be maintained when a database process or database management system stops and starts (e.g., during a restart).

Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.

This data-processing device includes a unit for processing data, a storage memory and a buffer-memory device configured to contain a first group of data relative to a first context and exchange data between the processing unit and the first group of data. The buffer-memory device is further configured to contain a second group of data relative to a second context and, upon reception of a context-switching instruction, exchange data between the processing unit and the second group of data, in place of the first group of data. The data-processing device further includes a context-switching device configured to emit the context-switching instruction, select a group of data recorded in the storage memory, copy the first group of data to the storage memory and copy the selected group of data to the buffer-memory device.

Technologies for providing accelerated functions as a service in a disaggregated architecture include a compute device that is to receive a request for an accelerated task. The task is associated with a kernel usable by an accelerator sled communicatively coupled to the compute device to execute the task. The compute device is further to determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request. Additionally, the compute device is to assign the task to the determined accelerator sled for execution. Other embodiments are also described and claimed.

A computing system may include a server configured to host virtual computing sessions, and a client device. The client device may be configured to remotely access a virtual computing session from the server, and receive user input data associated with the virtual computing session and classify the data into first (higher priority) and second (lower priority) data packets. The client device may also be configured to send the first data packets to the server via a first virtual channel, and send the second data packets to the server via a second virtual channel having a higher packet loss rate associated therewith than the first virtual channel. The server may be configured to assemble the second data packets to reconstruct and inject the user input data into the virtual computing session based upon the first data packets.

A system controlling method according to an embodiment of the present invention comprises operating a plurality of agents having mutually independent processes using a shared memory; obtaining hardware control data for controlling one or more devices from each of references generated from the plurality of agents and stored in the shared memory; and transferring control signals according to the references to the one or more devices selected from the hardware control data.

A system includes a memory buffer, a first data processor, a second data processor, and a controller. The first data processor performs a write operation to write data into the memory buffer and provides a first reference indicating a status or progress of the write operation. The controller provides a second reference indicating a buffer block in the memory buffer. The second data processor receives the first reference and the second reference, uses a threshold and the first reference to determine whether the buffer block contains enough data to be processed by the second data processor, obtains data to be processed from the buffer block using the second reference if the buffer block contains enough data to be processed, and processes the data obtained from the buffer block.

Various approaches for coordinating edge computing transactions are described, based on the generation and verification of fine-grained timestamp values among distributed computing entities in an edge computing system. In an edge computing system, an edge computing device performs operations to obtain transaction data, a timestamp, and a timestamp signature for a transaction, with the timestamp generated from a secure (and attestable) timestamp procedure that is coordinated with another entity (including via a network-coordinated timestamp synchronization). This timestamp is verified by the device based on the timestamp signature and the transaction data for the transaction, and the transaction is conducted (e.g., using a value of the timestamp) at the device or elsewhere in the system based on successful verification. In further examples, the coordinated timestamp enables multi-version concurrency control (MVCC) database transactions, verification of blockchain transactions, or other uses and verifications of timestamp values.

In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

An apparatus including a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache.