A data storage device includes a storage and a controller. The controller includes a storage region management circuit configured to manage the storage as plurality of logical storage regions, each corresponding to respective one of the groups of physical storage regions; an address conversion circuit configured to generate physical address including logical storage region address indicating one of the logical storage regions based on logical address; reference table configured to store relationship information among logical storage region address, physical location information indicating physical storage region corresponding to logical storage region indicated by the logical storage region address, and selection signal for activating the physical storage region; and a virtual address control circuit configured to generate the selection signal based on the logical storage region address in the physical address by referring to the reference table and transmit the selection signal and the physical address to the storage through the channel.

A processor executes firmware to write control data describing transfer descriptors for a bus protocol engine to an address that is associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine performs an operation according to the transfer descriptors with a slave device; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package other than the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. A first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.

A tensor traversal engine in a processor system comprising a source memory component and a destination memory component, the tensor traversal engine comprising: a control signal register storing a control signal for a strided data transfer operation from the source memory component to the destination memory component, the control signal comprising an initial source address, an initial destination address, a first source stride length in a first dimension, and a first source stride count in the first dimension; a source address register communicatively coupled to the control signal register; a destination address register communicatively coupled to the control signal register; a first source stride counter communicatively coupled to the control signal register; and control logic communicatively coupled to the control signal register, the source address register, and the first source stride counter.

Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.

A method including invoking, via an application, a call of a command line utility; providing, via the application, an identifier in the call of the command line utility, where the identifier comprises an operating system controlled memory location; storing output from the command line utility in operating system shared memory at the operating system controlled memory location identified by the identifier; and retrieving, by the application, the command line utility output from the operating system shared memory at the operating system controlled memory location identified by the identifier.

Methods, nodes, and a system for process scheduling, as well as corresponding computer programs and computer-program products.

A method for operating a control unit, in particular for a motor vehicle, the control unit including at least one execution unit for executing task programs, a first task program and a second task program being executed at least intermittently, the first task program providing data for the second task program at the end of a first predefined time interval, wherein a transfer of the data from the first task program to the second task program only takes place after a particular last execution of the first task program within a predefined second time interval for the execution of the second task program, the second time interval being longer than the first time interval.

Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.

A system and method is provided for timely and uniform real-time data packet transmission by a computing device. The system can include a shared packet memory buffer for storing data packets generated by a user application and a shared schedule memory buffer for storing packet identifiers and corresponding time slots for the data packets. Moreover, a kernel module is provided that operates in the kernel mode of the operating system directly above the network interface controller and can continuously poll the shared scheduled memory to access packet identifiers at corresponding time slots. Based on the packet identifiers in each time slot, the kernel module can pull the data packet having the packet identifier directly from the ring buffer and send each packet to the network interface controller for transmission as part of a media stream over a network to a media consuming device.

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.