The present application discloses a blockchain consensus method and device. In the blockchain consensus method, a blockchain node obtains service data on which to perform consensus processing. A service type of the service data is determined. At least one consensus node that provides a consensus service is selected by the blockchain node and from a consensus network based on the service type. The blockchain node sends the service data to the at least one consensus node, so that the at least one consensus node performs consensus processing on the service data.

A computer-implemented method and related systems for reducing memory access stalls and memory allocation requests in data-intensive applications are provided. Invariants associated with execution paths that access data in a memory of the data-intensive application are identified. At least one field specialization technique using at least one speccode segment is then applied. The speccode segment exploits the identified invariants, thereby reducing at least one of memory stalls and memory allocation requests in a data-intensive application. The field specialization technique may include specialized software prefetching, a data distribution-based hash function, process to CPU binding, memory segment reuse, or memory layout optimization, or any combination thereof.

A processor chip including a memory controller, application processor and a communication processor, where the memory controller is configured to define an area of memory as secure memory, and allow only an access request with a security attribute to access the secure memory. The application processor is configured to invoke a secure application in a trusted execution environment, and write an instruction request for a secure element into the secure memory using the secure application. The communication processor is configured to read the instruction request from the secure memory in the trusted execution environment, and send the instruction request to the secure element. The application processor and the communication processor need to be in the trusted execution environment when accessing the secure memory, and access the secure memory only using the secure application.

Technologies for providing efficient reprovisioning in an accelerator device include an accelerator sled. The accelerator sled includes a memory and an accelerator device coupled to the memory. The accelerator device is to configure itself with a first bit stream to establish a first kernel, execute the first kernel to produce output data, write the output data to the memory, configure itself with a second bit stream to establish a second kernel, and execute the second kernel with the output data in the memory used as input data to the second kernel. Other embodiments are also described and claimed.

In some aspects, a hybrid quantum-classical computing platform may comprise: a first quantum processor unit (QPU); a second QPU; and a shared classical memory, the shared classical memory being connected to both the first QPU and the second QPU, wherein the shared classical memory is configured to share data between the first QPU and the second QPU. In some embodiments, the first QPU operates at a higher repetition rate and/or clock rate than the second QPU and the second QPU operates with a higher fidelity than the first QPU.

An inference engine circuit architecture is disclosed which includes a matrix-matrix (MM) processor circuit and a MM accelerator circuit having multiple operating modes to provide a complete matrix multiplication. A representative MM accelerator circuit includes a first buffer circuit storing maps data; a first data network; multiple second buffer circuits each storing different kernel data; multiple second, serial data networks, with each coupled to a corresponding second buffer circuit; and a plurality of vector-vector (VV) acceleration circuits arranged in a plurality of arrays. Each VV acceleration circuit includes multiply and accumulate circuits; a shift register; a control multiplexer to provide a selected output, in response to a mode control word, of a bias parameter or a first accumulation sum; and a second adder circuit which adds the multiplicative product to the bias parameter or to the first accumulation sum to generate a second or next accumulation sum.

Methods and systems for maintaining validity of a memory model in a multiple core computer system are described. A first core prevents a store instruction from being performed by another core until a condition is met which enables reordered instructions to validly execute.

A data access method. The method is applied to a first controller, and the method includes: receiving a destination address sent by each shared cache apparatus, where the destination address is used to indicate an address at which data is to be written into the shared cache apparatus; receiving information carrying the data; and sending the destination address and the data to the shared cache apparatus that sends the destination address, so that each shared cache apparatus stores the data in storage space to which the destination address points.

Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.

A data management controller for a data processing system, the data processing system being capable of running one or more user space applications, each user space application defining: (i) one or more interface storage locations with which the data management controller can interact, each interface storage location being capable of storing interface data; and (ii) one or more services for processing data, each service interacting with at least one interface storage location during a processing run; the data management controller being configured to: (i) register each of the interface storage locations as an input data location or an output data location in response to the user space application so identifying the respective interface storage location to the data management controller; (ii) register the output data locations of user space applications as designated inputs to input data locations of one or more other user space applications; and (iii) in response to a user space application signalling that a processing run of a service is complete, initiate copying of the interface data stored in the output data locations with which that user space application interacts to the input data locations to which those output data locations are the designated inputs.