Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

This disclosure provides a cache replacing method applied to a heterogeneous multi-core system, the method including: determining whether a first application currently running is an application running on the GPU; when it is determined that the first application currently running is an application running on the GPU, determining a cache priority of first data accessed by the first application according to a performance parameter of the first application, the cache priority of the first data including a priority other than a predefined highest cache priority; and caching the first data into a cache queue of the shared cache according to a predetermined cache replacement algorithm and the cache priority of the first data, and replacing data in the cache queue.

The objective of the present invention is to prevent a conflict between variable names and consequently the unintentional overwriting of data when a plurality of programs that define a shared variable exist. A control device (1) is equipped with a program management part (11), a data storage part (13a), and a shared variable symbol table (13b). The program management part (11) acquires an identifier for a first user program, generates a shared variable name that includes the identifier and a variable name of a shared variable defined in the first user program, associates the shared variable name and an address of the shared variable with each other, and records these in the shared variable symbol table (13b).

A control system including a control device and a development supporting device for developing a plurality of programming languages executed in the control device, wherein the development supporting device includes an input unit that inputs source codes of the plurality of different programming languages, a mapping information producing unit that performs mapping of shared variables selected in the source codes, respectively, and that produces shared variable mapping information, and a transmit unit that transmits source codes and shared variable mapping information to the control device, wherein the control device includes a program executing unit that executes programs described by source codes, and a shared variable processing unit that processes each of mapped shared variables as common shared variables based on shared variable mapping information.

A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.

Embodiments of the present disclosure provides systems and methods for batch accessing. The system includes a plurality of buffers configured to store data; a plurality of processor cores that each have a corresponding buffer of the plurality of buffers; a buffer controller configured to generate instructions for performing a plurality of buffer transactions on at least some buffers of the plurality of buffers; and a plurality of data managers communicatively coupled to the buffer controller, each data manager is coupled to a corresponding buffer of the plurality of buffers and configured to execute a request for a buffer transaction at the corresponding buffer according to an instruction received from the buffer controller.

Aspects of the disclosure track and monitor automated system events, user-initiated events, and outcomes associated with system events and user-initiated events for providing real-time or near real-time measurements and insights. According to examples, a system is provided that is operative or configured to collect specific events and associated data associated with events that occur within various systems and products. The data is captured, aggregated, and stored in in-memory data storage. Accordingly, the data can be represented and displayed in a dashboard interface in real-time or near real-time. Accordingly, inefficient polling, long-running queries, and scheduled tasks can be eliminated.

A workflow engine tool is disclosed that enables scientists and engineers to programmatically author workflows (e.g., a directed acyclic graph, “DAG”) with nearly no overhead, using a simpler script that needs almost no modifications for portability among multiple different workflow engines. This permits users to focus on the business logic of the project, avoiding the distracting tedious overhead related to workflow management (such as uploading modules, drawing edges, setting parameters, and other tasks). The workflow engine tool provides an abstraction layer on top of workflow engines, introducing a binding function that converts a programming language function (e.g., a normal python function) into a workflow module definition. The workflow engine tool infers module instances and induces edge dependencies automatically by inferring from a programming language script to build a DAG.

A system for secure data transfer using air gapping. A first module includes: a first module communication interface configured to communicate with a public network. A second module includes: a first read-only memory storing an operating system; a second read-only memory storing sets of private keys of the second module and at least one public key of another remote entity; a cryptographic unit configured to encrypt and/or decrypt data using the keys stored in the second read-only memory. A bridge module includes: a bridge module controller; memory for storing data; a switch configured to selectively connect the bridge module data interface to either the first module data interface or to the second module data interface such that the first module data interface is never connected with the second module data interface.

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.