Briefly, an encryption/decryption algorithm providing for consistent encryption entropy and encryption/decryption performance that is independent of the type of input data.

A buffer summary group of a plurality of buffer summary groups is accessed. The buffer summary group includes one or more summary indicators for one or more buffers assigned to the buffer summary group. A summary indicator of the one or more summary indicators of the buffer summary group is checked to determine whether an event has occurred for at least one buffer of the one or more buffers assigned to the buffer summary group. Based on the checking indicating that the event has occurred, one or more actions are performed.

Techniques for task processing based on load latency amelioration using bunch buffers are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide control words generated by the compiler. Sets of control word bits are loaded into buffers. Each buffer is associated with and coupled to a unique compute element within the array of compute elements. The sets of control word bits provide operational control for the compute element with which it is associated. Operations are executed within the array of elements. The operations are based on a selected set of control word bits which comprise a control word bunch.

A data structure for a jointly utilized memory device, in particular, for inter-process communication, in an application system. The memory device includes a memory cell. The data structure includes a management structure, the management structure being configured to hold a pointer object to the memory cell.

This disclosure describes methods, devices, systems, and procedures in a computing system for capturing a configuration state of an operating system executing on a central processing unit (CPU), and offloading resource-related tasks, based on the configuration state, to a resource management unit such as a system-on-chip (SoC). The resource management unit identifies a status of each resource based on the captured configuration state of the operating system. The resource management unit then processes tasks associated with the status of the resources, such as modifying a clock rate of a clocked component in the computing system. This can alleviate the CPU from processing those tasks thereby improving overall computing system performance and dynamics.

The field of high-speed data acquisition and network data processing, and particularly relates to an Ethernet data stream recording method, an Ethernet data stream recording system, and an Ethernet data stream recording device for a high-speed data acquisition system. It is intended to solve problems such as a low utilization rate of CPU, poor system compatibility, difficulty in packaging and deployment and low reliability of system transmission of the traditional high-speed data acquisition system. The method of the present disclosure includes: isolating a preset number of CPU cores after a Linux operating system is booted; uninstalling a kernel network card driver of the operating system and creating a hugepage memory pool; for each 10-gigabit network card, allocating a corresponding data-receiving buffer pool and a corresponding lock-free FIFO buffer, and initializing a PCIE register of each 10 gigabit network card such that each 10-gigabit network card enters into an acquisition state; and continuously receiving packets acquired by each 10 gigabit network card in a driving manner of user space polling and performing disk recording. According to the present disclosure, the utilization rate of CPU, system compatibility and transmission reliability are improved and the difficulty in packaging and deployment is decreased.

Example techniques related to portable playback device power management. An example implementation involves launching a power coordinator background process, the power coordinator background process having multiple client programs and establishing respective inter-process communication (IPC) mechanisms between the multiple client programs and the power coordinator background process. The implementation further involves receiving, via the established IPC mechanisms from the multiple client programs, messages indicating that the respective client program is ready to suspend, and determining that each client program of the multiple client programs is ready to suspend. The implementation further includes sending instructions to the operating system to kernel suspend. While in kernel suspend, the playback device detects a particular trigger to kernel resume and in response, performs a kernel resume.

A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.

The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors and an inter-processor communication (IPC) unit. The IPC unit includes one or more doorbell registers, wherein each doorbell register is associated with a uniquely assigned source processor and a uniquely assigned target processor. Each doorbell register is further configured to store doorbell data indicative of whether an interrupt is a high priority interrupt or a low priority interrupt. The IPC unit may also include one or more FIFO (first-in first-out) memories configured to store data associated with each interrupt.

An image signal processor includes a line interleaving controller and an image signal processor core. The line interleaving controller receives a plurality of image data lines included in an image frame, generates one or more virtual data lines corresponding to the image frame, and outputs the plurality of image data lines and the virtual data lines sequentially line by line. The image signal processor core includes at least one pipeline circuit. The pipe line circuit includes a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller. The line interleaving controller processes one or more end image data lines included in an end portion of the image frame based on the virtual data lines. Interference or collision between channels is reduced or prevented by processing the end image data lines in synchronization with the virtual data lines.