Systems and methods are described for processing ingested data in an asynchronous manner as the data is being ingested to detect potential anomalies. For example, one or more streaming data processors can convert data as the data is ingested into a comparable data structure, determine whether the comparable data structure should be assigned to an existing data pattern or a new data pattern, and optionally update a characteristic of the data pattern to which the comparable data structure is assigned. The streaming data processor(s) can perform these operations automatically in real-time or in periodic batches. Once one or more comparable data structures have been assigned to one or more data patterns, the streaming data processor(s) can analyze the comparable data structures assigned to a particular data pattern to determine whether any of the comparable data structures appear to be anomalous.

Data processing apparatuses, methods of data processing, complementary instructions and programs related to ring buffer administration are disclosed. An enqueuing operation performs an atomic compare-and-swap oper-ation to store a first processed data item indication to an enqueuing-target slot in the ring buffer contingent on an in-order marker not being present there and, when successful, determines that a ready-to-dequeue condition is true for the first processed data item indication. A dequeuing operation, when the ready-to-de-queue condition for a dequeuing-target slot is true, comprises writing a null data item to the dequeuing-target slot and, when dequeuing in-order, further comprises, dependent on whether a next contiguous slot has null content, determining a retirement condition and, when the retirement condition is true, performing a retirement process on the next contiguous slot comprising making the next con-tiguous slot available to a subsequent enqueuing operation. Further subsequent slots may also be retired.

A processor comprises a core, a cache, and a ZCM manager in communication with the core and the cache. In response to an access request from a first software component, wherein the access request involves a memory address within a cache line, the ZCM manager is to (a) compare an OTAG associated with the memory address against a first ITAG for the first software component, (b) if the OTAG matches the first ITAG, complete the access request, and (c) if the OTAG does not match the first ITAG, abort the access request. Also, in response to a send request from the first software component, the ZCM manager is to change the OTAG associated with the memory address to match a second ITAG for a second software component. Other embodiments are described and claimed.

A memory allocation device for deployment within a host server computer includes control circuitry, a first interface to a local processing unit disposed within the host computer and local operating memory disposed within the host computer, and a second interface to a remote computer. The control circuitry allocates a first portion of the local memory to a first process executed by the local processing unit and transmits, to the remote computer via the second interface, a request to allocate to a second process executed by the local processing unit a first portion of a remote memory disposed within the remote computer. The control circuitry further receives instructions via the first interface to store data at a memory address within the first portion of the remote memory and transmits those instructions to the remote computer via the second interface.

A tensor traversal engine in a processor system comprising a source memory component and a destination memory component, the tensor traversal engine comprising: a control signal register storing a control signal for a strided data transfer operation from the source memory component to the destination memory component, the control signal comprising an initial source address, an initial destination address, a first source stride length in a first dimension, and a first source stride count in the first dimension; a source address register communicatively coupled to the control signal register; a destination address register communicatively coupled to the control signal register; a first source stride counter communicatively coupled to the control signal register; and control logic communicatively coupled to the control signal register, the source address register, and the first source stride counter.

In an embodiment, a system includes a plurality of memory components and a processing device that is operatively coupled with the plurality of memory components. The processing device includes a host interface, an access management component, a media management component (MMC), and an MMC-restart manager that is configured to perform operations including detecting a triggering event for restarting the MMC, and responsively performing MMC-restart operations that include suspending operation of the access management component; determining whether the MMC is operating, and if so then suspending operation of the MMC; resetting the MMC; resuming operation of the MMC; and resuming operation of the access management component.

Devices and techniques for pipeline merging in a circuit are described herein. A parallel pipeline result can be obtained for a transaction index of a parallel pipeline. Here, the parallel pipeline is one of several parallel pipelines that share transaction indices. An element in a vector can be marked. The element corresponds to the transaction index. The vector is one of several vectors respectively assigned to the several parallel pipelines. Further each element in the several vectors corresponds to a possible transaction index with respective elements between vectors corresponding to the same transaction index. Elements between the several vectors that correspond to the same transaction index can be compared to determine when a transaction is complete. In response to the transaction being complete, the result can be released to an output buffer in response to the transaction being complete.

A method for operating a computing device for a control unit of a motor vehicle. The computing device including a processor core, and is configured to control an exchange of data between a connectivity zone and a security zone. The security zone includes at least one component which is necessary to drive the vehicle and has an elevated relevance with regard to safety. The connectivity zone including at least one component whose operation requires communication outside of the vehicle but is not required to drive the vehicle and does not have an elevated relevance with regard to safety. At least one first program executable by the computing device is assigned to a non-trustworthy zone, and at least one further program is assigned to a trustworthy zone. The component of the connectivity zone is assigned to the non-trustworthy zone, and the component of the security zone being assigned to the trustworthy zone.

A system on chip and a method for operating a system on chip are provided. The system on chip a plurality of intellectual property (IP) cores including a first IP core configured to process data in real-time, a buffer including a plurality of queues, and processing circuitry configured to, generate first traffic data corresponding to first data output from the first IP core, and reserve at least one queue of the plurality of queues as a first dedicated area based on the first traffic data, the first dedicated area configured to be used as a queue for transmission of the first data.

Technologies include an interface processor configured to be communicatively coupled to a memory and a first processor. The interface processor is to obtain, from a first module compiled from a first software language, first data having a first native type of the first software language. The interface processor is further to convert the first data into second data having a first interface type, convert the second data having the first interface type into third data having a second native type of a second software language, and provide the third data to a second module associated with the second software language. The first software language may be compiled to WebAssembly binary code. The second software language may also be compiled to WebAssembly binary code and may be different than the first software language.