A system for collaborative execution of a task includes a plurality of edge units in communication with a principal processor. Each edge unit includes a collaborative intelligence module configured to establish a communication link amongst at least two of the edge units. The communication intelligence module is further configured to communicate task attributes of the task with at least one other edge unit, and to exchange sensor data from the set of sensors and a plan with the at least one other edge unit to create a joint workspace followed by execution of the task in collaboration with the at least one other edge unit.

A computer implemented method for managing buffer pool usage includes identifying a database comprising one or more buffer pools and a set of database objects, adding a virtual layer between the set of database objects and the one or more buffer pools, wherein the virtual layer is configured to manage buffer pool resource utilization, managing, using the added virtual layer, buffer pool resource utilization with respect to the set of database objects, wherein the managing comprises defining buffer pool usage corresponding to the set of database objects, dynamically mapping database objects to the buffer pools based, at least in part, on the defined buffer pool usage, analyzing, by one or more processors, queues to identify updated buffer pool usage, and adjusting database object allocation according to the identified updated resource usage. A computer program product and computer system corresponding to the method are also disclosed.

A method executes inter-enclave communication via cache memory of a processor. The method includes: instantiating a first enclave such that it is configured to execute a first communication thread, which is configured to read/write data to the cache memory; instantiating a second enclave such that it is configured to execute a second communication thread, which is configured to read/write data to cache memory; executing, by the first enclave, the first communication thread to send message data to the second enclave, executing the first communication thread comprising writing the message data to the cache memory; and executing, by the second enclave, the second communication thread to receive the message data. Executing the second communication thread can include: monitoring the cache memory to determine whether the data message is being sent; and based upon determining the data message is being sent, reading from the cache memory to receive the data message.

Systems and methods are described for processing ingested data, detecting anomalies in the ingested data, and providing explanations of a possible cause of the detected anomalies as the data is being ingested. For example, a token or field in the ingested data may have an anomalous value. Tokens or fields from another portion of the ingested data can be extracted and analyzed to determine whether there is any correlation between the values of the extracted tokens or fields and the anomalous token or field having an anomalous value. If a correlation is detected, this information can be surfaced to a user.

An encryption specification named “MetaEncrypt” implemented as a method and associated apparatus is disclosed for unbreakable encryption of data, code, applications, and other information that uses a symmetric key for encryption/decryption and to configure the underlying encryption algorithms being utilized to increase the difficulty of mathematically modeling the algorithms without possession of the key. Data from the key is utilized to select several encryption algorithms utilized by MetaEncrypt and configure the algorithms during the encryption process in which block sizes are varied and the encryption technique that is applied is varied for each block. Rather than utilizing a fixed key of predetermined length, the key in MetaEncrypt can be any length so both the key length and key content are unknown. MetaEncrypt's utilization of key data makes it impossible to model its encryption methodology to thereby frustrate cryptographic cracking and force would be hackers to utilize brute force methods to try to guess or otherwise determine the key.

An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.

Methods, systems, and computer program products for determining optimal compute resources for distributed batch based optimization applications are provided herein. A method includes obtaining a size of an input dataset, a size of a model, and a set of batch sizes corresponding to a job to be processed using a distributed computing system; computing, based at least in part on the set of batch sizes, one or more node counts corresponding to a number of nodes that can be used for processing said job; estimating, for each given one of the node counts, an execution time to process the job based on an average computation time for a batch of said input dataset and an average communication time for said batch of said input dataset; and selecting, based at least in part on said estimating, at least one of said node counts for processing the job.

The present disclosure relates to methods and apparatus for machine learning processing. For example, disclosed techniques facilitate improving execution of machine learning primitives. Aspects of the present disclosure may store a command stream generated by an application in a buffer, the command stream including a plurality of machine learning primitives for execution by a graphics processor. Further, aspects of the present disclosure identify, after receiving a request from the application to finalize the buffer, two or more machine learning primitives of the buffer that may be replaced with a fused shader kernel. Additionally, aspects of the present disclosure may store the fused shader kernel in the buffer to generate a fused command buffer.

A supervisory control system provides power management in an electronic device by providing timeout periods for a hardware component to lower levels of the operating system such as a power management arbitrator and/or a hardware interface controller. The power management arbitrator and/or hardware interface controller transition at least a portion of a hardware component to a lower-power state based on monitored activity information of the hardware component. The supervisory control system may further provide wakeup periods to the power management arbitrator and/or a hardware interface controller to determine whether the hardware component should be transitioned to a higher-power state at the end of the wakeup period if the hardware component satisfies a transition condition.

In one embodiment, an apparatus includes: a plurality of queues having a plurality of first entries to store receive information for a process; a master queue having a plurality of second entries to store wild card receive information, where redundant information of the plurality of second entries is to be included in a plurality of redundant entries of the plurality of queues; and a control circuit to match an incoming receive operation within one of the plurality of queues. Other embodiments are described and claimed.