Patent classifications
G06F9/544
LOW LATENCY STREAMING REMAPPING ENGINE
A lens distortion correction function operates by backmapping output images to the uncorrected, distorted input images. As a vision image processor completes processing on the image data lines needed for the lens distortion correction function to operate on a group of output, undistorted image lines, the lens distortion correction function begins processing the image data. This improves image processing pipeline delays by overlapping the operations. The vision image processor provides output image data to a circular buffer in SRAM, rather than providing it to DRAM. The lens distortion correction function operates from the image data in the circular buffer. By operating from the SRAM circular buffer, access to the DRAM for the highly fragmented backmapping image data read operations is removed, improving available DRAM bandwidth. By using a circular buffer, less space is needed in the SRAM. The improved memory operations further improve the image processing pipeline delays.
TELEMATICS SYSTEM FOR IDENTIFYING MANUFACTURER-SPECIFIC CONTROLLER-AREA NETWORK DATA
Methods and systems for identifying manufacturer-specific controller-area (CAN) data for a vehicle type are provided. Manufacturer-specific CAN data may be identified by processing defined CAN data having a correlation relationship with the target data and undefined manufacturer-specific CAN data for determining if there is a correlation relationship therebetween. Also provided are methods and systems for identifying and automatically collecting manufacturer-specific CAN data for a vehicle type.
EVENT HANDLING IN PIPELINE EXECUTE STAGES
A method includes receiving an execute packet that includes a first instruction and a second instruction and executing the first instruction and the second instruction using a pipeline. Executing the first and second instructions includes storing a result of the first instruction in a holding register; determining whether an event that interrupts execution of the execute packet occurs prior to completion of the executing of the second instruction; and based on the event not occurring, committing the result of the first instruction after completion of the executing of the second instruction.
Network system, network node and communication method
Network system being configured to execute I/O commands and application commands in parallel and comprising a network and at least one network node, wherein the at least one network node is connected to the network via a network adapter and is configured to run several processes and/or threads in parallel, wherein the at least one network node comprises or is configured to establish a common communication channel (C-channel) to be used by the several processes and/or threads for data communication with the network via the network adapter, wherein the C-channel comprises or is established to comprise a work queue (WQ) for execution of I/O commands and a completion queue (CQ) for indication of a status of I/O commands, and wherein the at least one network node, especially its comprised or to be established C-channel, is configured for an exclusive access of precisely one single process or thread out of the several processes and/or threads to the CQ of the C-channel at a particular time.
Dynamically changing configuration of data processing unit when connected to storage device or computing device
In one example, a data processing unit (DPU) includes a host unit interface for communicatively coupling to second device via a serial input/output (I/O) connection, and a control unit implemented in circuitry and configured to initially configure the host unit interface of a data processing unit to operate in endpoint mode, determine that the host unit interface of the data processing unit is to switch from operating in the endpoint mode to root complex mode, in response to determining that the host unit interface is to switch from operating in the endpoint mode to the root complex mode: configure the host unit interface to operate in the root complex mode, and send data to an I/O expander unit to cause the I/O expander unit to issue a reset signal to the second device, the second device being configured to operate in the endpoint mode.
Method and apparatus for processing data and computer system
A method and an apparatus for processing data and a computer system are provided. The method includes copying a shared virtual memory page to which a first process requests access into off-chip memory of a computing node, and using the shared virtual memory page copied into the off-chip memory as a working page of the first process; and before the first process performs a write operation on the working page, creating, in on-chip memory of the computing node, a backup page of the working page, so as to back up original data of the working page. Before a write operation is performed on a working page, page data is backed up in the on-chip memory, so as to ensure data consistency when multiple processes perform an operation on a shared virtual memory page while accessing off-chip memory as less as possible and improving a speed of a program.
Multi-tenant data protection in edge computing environments
In an edge computing system deployment, a system includes memory and processing circuitry coupled to the memory. The processing circuitry is configured to obtain a workflow execution plan that includes workload metadata defining a plurality of workloads associated with a plurality of edge service instances executing respectively on one or more edge computing devices. The workload metadata is translated to obtain workload configuration information for the plurality of workloads. The workload configuration information identifies a plurality of memory access configurations and service authorizations identifying at least one edge service instance authorized to access one or more of the memory access configurations. The memory is partitioned into a plurality of shared memory regions using the memory access configurations. A memory access request for accessing one of the shared memory regions is processed based on the service authorizations.
Storage system
A storage system includes a first storage controller including a plurality of main storage media and one or more processor cores, and a second storage controller including a plurality of main storage media and one or more processor cores and performing communication with the first storage controller. Storage areas of the main storage media in the first storage controller are allocated to an address map. In response to the occurrence of failures in one or mode main storage media of the main storage media of the first storage controller, the first storage controller performs restarting to reallocate the storage areas of the main storage media excluding one or more main storage media having caused the failures to an address map reduced than before the occurrence of the failures. The second storage controller continues operating during the restarting of the first storage controller.
Systems and methods for management of multi-tenancy data analytics platforms
A data analytics system configured to perform operations is disclosed. The operations can include creating, in response to instructions received from a user, a first pipeline. This pipeline can be configured to extract data from an append-only first data store, extract identifying characteristics from the extracted data, provide the identifying characteristics to an identity service, and receive a tenancy identifier from the identity service. The pipeline can further be configured to create a data object in a second data store using the extracted data; create a tenancy object in a metadata store, the tenancy object associated with the data object, the metadata store implementing a hierarchical data object ownership graph; and associate the tenancy object with a parent object in the hierarchical data object ownership graph. The data analytics system can then tear down the first pipeline.
Neural network processing assist instruction
A first processor processes an instruction configured to perform a plurality of functions. The plurality of functions includes one or more functions to operate on one or more tensors. A determination is made of a function of the plurality of functions to be performed. The first processor provides to a second processor information related to the function. The second processor is to perform the function. The first processor and the second processor share memory providing memory coherence.