During operation, the system receives a chunk of data to be written to a non-volatile memory, wherein the chunk includes a plurality of sectors. The system assigns consecutive logical block addresses (LBAs) to the plurality of sectors. In response to determining that a first sector is associated with an existing stream for the chunk, the system appends the first sector to one or more other sectors stored in a first buffer associated with the existing stream. The system detects that a total size of the stored sectors in the first buffer is the same as a first size of a physical page in the non-volatile memory. The system writes the stored sectors from the first buffer to the non-volatile memory at a first physical page address. The system creates, in a data structure, a first entry which maps the LBAs of the written sectors to the first physical page address.

A method for tracking and/or characterizing multiple objects in a sequence of images. The method includes: assigning a neural network to each object to be tracked; providing a memory shared by all neural networks, and designed to map an address vector of address components, via differentiable operations, onto one or multiple memory locations, and to read data from these memory locations or write data into these memory locations; supplying images from the sequence, and/or details of these images, to each neural network; during the processing of each image and/or image detail by one of the neural networks, generating an address vector from at least one processing product of this neural network; based on this address vector, writing at least one further processing product of the neural network into the shared memory, and/or reading out data from this shared memory and further processing the data by the neural network.

A method for tracking and/or characterizing multiple objects in a sequence of images. The method includes: assigning a neural network to each object to be tracked; providing a memory that is shared by all neural networks; providing a local memory for each neural network, respectively; supplying images from the sequence, and/or details of these images, to each neural network; during the processing of each image and/or image detail by one of the neural networks, generating an address vector from at least one processing product of this neural network; based on this address vector, writing at least one further processing product of the neural network into the shared memory and/or into the local memory, and/or reading out data from this shared memory and/or local memory and further processing the data by the neural network.

Systems and methods are provided for automatically orchestrating the handling of events through a processing pipeline without limitation (or without a substantial limitation) as to the size of the event payload associated with the event. The event pipeline system stores event payloads in data stores and generates notifications regarding the events. The notifications may be placed into event streams for handling by various processing components of the event pipeline system. The processing components may receive notifications or events that they are to process, and may separately access event payloads from the data stores. The processing components may generate and save processed event payloads to the data stores in a streaming fashion such that the computing resources of the processing components do not limit (or substantially limit) the size of the event payloads that the processing components may handle.

A method includes generating a rule unit as a containerized microservice on a cloud platform. The method further includes deploying, by a processing device, the containerized microservice on a container platform. The method further includes enabling message passing between the containerized microservice and additional containerized microservices over a shared channel.

Some embodiments provide a novel method for splicing Transmission Control Protocol (TCP) sockets on a computing device that processes a kernel of an operating system. The method receives a set of packets at a first TCP socket of the kernel. The method stores the set of packets at a kernel memory location sends the set of packets directly from the kernel memory location out through a second TCP socket of the kernel.

Methods and systems for communicating information between mobile applications are presented. In some embodiments, a mobile device may determine that a plurality of applications are running on the mobile device. The mobile device may determine that each application of the plurality of applications uses a shared passcode to encrypt information about a persistent state. The mobile device may generate a beacon that includes encrypted state information. The mobile device may maintain state information across the plurality of applications beyond the lifetime of any one of the plurality of applications by transmitting the beacon from a first application to a second application before the first application's lifetime is completed.

A memory system having a set of media, a plurality of inter-process communication channels, and a controller configured to run a plurality of processes that communicate with each other using inter-process communication messages transmitted via the plurality of inter-process communication channels, in response to requests from a host system to store data in the media or retrieve data from the media. The memory system has a message manager that examines requests from the host system, identifies a plurality of combinable requests, generates a combined request, and provides the combined request to the plurality of processes as a substitute of the plurality of combinable requests.

A GPU includes one or more post-processing controllers, and a 3D graphics pipeline including a post-processing shader stage following a pixel shader stage. The one or more post-processing controllers may synchronize an execution of one or more post-processing stages including the post-processing shader stage. The 3D pipeline may include one or more pixel shaders, one or more tile buffers, and a direct communication link between the post-processing shader stage and the one or more tile buffers. The one or more post-processing controllers may synchronize communication between the one or more post-processing shaders and the one or more tile buffers.

Systems and methods of error handling in a network interface card (NIC) are provided. For a data packet destined for a local virtual machine (VM), if the NIC cannot determine a valid translation memory address for a virtual memory address in a buffer descriptor from a receive queue of the VM, the NIC can retrieve a backup buffer descriptor from a hypervisor queue, and store the packet in a host memory location indicated by an address in the backup buffer descriptor. For a transmission request from a local VM, if the NIC cannot determine a valid translated address for a virtual memory address in the packet descriptor from a transmit queue of the VM, the NIC can send a message to a hypervisor backup queue, and generate and transmit a data packet based on data in a memory page reallocated by the hypervisor.