Methods, systems, and computer program products for parameter management between programs with different addressing modes are described. A request may be received from a first program with a first addressing mode in a first runtime environment for calling a second program with a second addressing mode different from the first addressing mode, where at least one parameter included in the request is for calling the second program. A parameter area may be allocated in the first runtime environment for the at least one parameter. The at least one parameter may be stored in the allocated parameter area. The second program may be invoked based at least in part on the at least one parameter in the allocated parameter area. In this manner, parameter(s) may be communicated between the first program and the second program in an easy and effective way.

A hypervisor executing on a computer system identifies a request of a guest operating system of a virtual machine associated with a shared device. The shared device comprises a shared memory space between a virtual processor of the virtual machine and the hypervisor and the virtual machine has a plurality of virtual processors. The hypervisor processes the request of the guest operating system and polls the shared device for additional requests of the guest operating system. Upon determining that there are no additional requests associated with the shared device to be processed, the hypervisor determines the execution state of each virtual processor of the virtual machine. The hypervisor disables polling the shared device for requests upon determining that at least one of the plurality of virtual processors has been pre-empted.

A Lock register can be associated with a mailbox. The Lock register can store a claim ID of a process that has allocated the mailbox. The Lock register can include a Lock port and a Lock Clear port, used to claim and release the Lock register. The Lock register only permits data to be written to the Lock Register when the Lock register is not currently allocated, and the Lock Clear port only permits the process that has allocated the Lock register to write a value.

Methods and systems for memory resource allocation are disclosed. In an embodiment, a method for memory resource allocation involves reading a pool-specific configuration record from an array of memory mapped pool-specific configuration records according to a memory resource allocation request that is held in an address register of a memory mapped register interface, performing a memory resource allocation operation to service the memory resource allocation request, wherein performing the memory resource allocation operation involves interacting with a resource list according to a pointer in the pool-specific configuration record, advancing the pointer after the interaction, and updating the pointer in the pool-specific configuration record with the advanced pointer.

A non-transitory computer-readable storage medium storing a replication program that causes a first information processing apparatus to execute a process, the process including storing update information to a first shared storage area of a first virtual machine, the update information indicating update of data stored in a storage area of a second virtual machine, when an additional update information is stored in the first shared storage area, transmitting the additional update information to a third virtual machine, and causing the third virtual machine to store the additional update information in a second shared storage area of the third virtual machine, the additional update information stored in the second shared storage area being used to update data stored in a storage area of the fourth virtual machine.

Systems and methods are disclosed for swapping or changing between stacks associated with respective applications when one application calls the other.

A multiprocessor system includes a first microprocessor and a second microprocessor. A first signaling pathway is configured to send message transmission coordination signals from the first microprocessor to the second microprocessor. The first signaling pathway may be coupled to at least two flag registers associated with the second microprocessor. A second signaling pathway is configured to send message transmission coordination signals from the second microprocessor to the first microprocessor. The second signaling pathway may be coupled to at least two flag registers associated with the first microprocessor. The first signaling pathway is independent of the second signaling pathway.

A multiprocessor system includes a first microprocessor and a second microprocessor. An external memory system is coupled to the first and second microprocessors and is configured to receive and temporarily store messages transferred between the first and second microprocessors. A first signaling pathway may be configured to send message transmission coordination signals from the first microprocessor to the second microprocessor. A second signaling pathway may be configured to send message transmission coordination signals from the second microprocessor to the first microprocessor. The first signaling pathway may be independent of the second signaling pathway. The first signaling pathway may be coupled to at least two flag registers associated with the second microprocessor. The second signaling pathway may be coupled to at least two flag registers associated with the first microprocessor.

An image and vision processing architecture included a plurality of image processing hardware accelerators each configured to perform a different one of a plurality of image processing operations on image data. A multi-port memory shared by the hardware accelerators stores the image data and is configurably coupled by a sparse crossbar interconnect to one or more of the hardware accelerators depending on a use case employed. The interconnect processes accesses of the image data by the hardware accelerators. Two or more of the hardware accelerators are chained to operate in sequence in a first order for a first use case, and at least one of the hardware accelerators is set to operate for a second use case. Portions of the memory are allocated to the hardware accelerators based on the use case employed, with an allocated portion of the memory configured as a circular buffer.

Techniques are disclosed relating to a shared control bus for communicating between primary control circuitry and multiple distributed graphics processor units. In some embodiments, a set of multiple processor units includes first and second graphics processors, where the first and second graphics processors are coupled to access graphics data via respective memory interfaces. A shared workload distribution bus is used to transmit control data that specifies graphics work distribution to the multiple graphics processing units. The shared workload distribution bus may be arranged in a chain topology, e.g., to connect the workload distribution circuitry to the first graphics processor and connect the first graphics processor to the second graphics processor such that the workload distribution circuitry communicates with the second graphics processor via the shared workload distribution bus connection to the first graphics processor. Disclosed techniques may facilitate graphics work distribution for a scalable number of processors.