Patent classifications
G06F9/544
OPERATION METHOD OF THE NON-UNIFORM MEMORY ACCESS SYSTEM
Provided is an operation method of a NUMA system, which includes: designating a page scan range including a plurality of pages; identifying a detour value for each of the plurality of pages; determining whether a detour value of a current target scan page is the same as the reference detour value; and releasing a connection of the current target scan page from the page table when determining that the detour value of the current target scan page is the same as the reference detour value.
Handling large messages via pointer and log
A computer system with a first messaging application communicates a message to another computer system with a second messaging application via a coupling facility storage device. If the message does not exceed a predetermined threshold, the message is put onto the queue in the coupling facility. If the message does exceed a predetermined threshold, the message is put onto a log associated with the first messaging application and readable by the second messaging application. A pointer to the message is put onto the queue in the coupling facility. The pointer can be used to access the message in the log.
SECURE VIRTUAL MACHINE AND PERIPHERAL DEVICE COMMUNICATION
A method includes exposing a public cryptographic key associated with a peripheral device of a computing system to a guest running on the computing system. The method further includes receiving, from the guest, a message including a cryptographic nonce value encrypted with the public cryptographic key. The method further includes producing the cryptographic nonce value by decrypting the message using a private cryptographic key associated with the public cryptographic key. The method further includes using a shared cryptographic key generated from the cryptographic nonce value to access contents of a direct memory access (DMA) buffer associated with the peripheral device.
Efficient high bandwidth shared memory architectures for parallel machine learning and AI processing of large data sets and streams
The present disclosure relates to systems and methods to implement efficient high-bandwidth shared memory systems particularly suited for parallelizing and operating large scale machine learning and AI computing systems necessary to efficiently process high volume data sets and streams.
High-speed scanning parser for scalable collection of statistics and use in preparing data for machine learning
A parser is deployed early in a machine learning pipeline to read raw data and collect useful statistics about the raw data's content to determine which items of raw data exhibit a proxy for feature importance for the machine learning model. The parser operates at high speeds that approach the disk's absolute throughput while utilizing a small memory footprint. Utilization of the parser enables the machine learning pipeline to receive a fraction of the total raw data that would otherwise be available. Several scans through the data are performed, by which proxies for feature importance are indicated and irrelevant features may be discarded and thereby not forwarded to the machine learning pipeline. This reduces the amount of memory and other hardware resources used at the server and also expedites the machine learning process.
Storage device and operating method thereof
A storage device includes a nonvolatile memory device that includes a first area, a second area, and a third area, and a controller that receives a write command and first data from a host device, preferentially writes the first data in the first area or the second area rather than the third area when the first data is associated with a turbo write, and writes the first data in the first area, the second area, or the third area when the first data is associated with a normal write. The controller moves second data between the first area, the second area, and the third area based on the policy received from the host device.
Dynamic link objects across different addressing modes
A call to an external interface to execute a target callee program associated with a first addressing mode in a secondary runtime environment (RTE) is received from a caller program associated with a second addressing mode running in a primary RTE. An address of a share area (SA) storing existing dynamic link object information in the primary RTE in storage is passed to the secondary RTE. The SA is accessible by both the caller program and the target callee program. In response to a request to load a dynamic link object by an initiating program during execution of the target callee program in the secondary RTE, an entry address of the dynamic link object is retrieved in the SA. The dynamic link object is loaded based on the retrieved entry address of the dynamic link object.
CONTAINER IN CONTAINER METHOD TO CONFINE PRIVILEGED MODE EXECUTION DURING HOST DATA EXCHANGE IN A CONTAINERIZED ENVIRONMENT
A disclosed method for implementing containers in an information handling system generates, with a first non-privileged container, a request that is sent to a RESTful API. Whenever the API identifies a request requiring host access the API launches a second container, which is configured to operate in a privileged execution mode. The second container accesses the host and executes the requested actions. When the request completes, the first container resumes non-privileged execution, thereby confining privileged mode execution to a container that is only active during host interaction. The host access can be access required to: exchange data with the host, query the host for hardware information, and modify host configuration. The host may be implanted within a device featuring an HCI infrastructure. In one configuration, the host resides of one of multiple distinct nodes of an HCI appliance.
Apparatus and method for writing data in a memory
A device for writing data to a memory, the device including: a first write buffer having a first data width that matches a width of write data included in a write request and wherein the first write buffer is configured to store the write data as first data; a second write buffer having a second data width that matches a data width of the memory and is greater than the first data width; and a controller configured to, based on a write address included in the write request and an address of the second data stored in the second write buffer, write the first data stored in the first write buffer to the second write buffer and write the second data stored in the second write buffer to the memory.
Lock-free work-stealing thread scheduler
Systems and methods are provided for lock-free thread scheduling. Threads may be placed in a ring buffer shared by all computer processing units (CPUs), e.g., in a node. A thread assigned to a CPU may be placed in the CPU's local run queue. However, when a CPU's local run queue is cleared, that CPU checks the shared ring buffer to determine if any threads are waiting to run on that CPU, and if so, the CPU pulls a batch of threads related to that ready-to-run thread to execute. If not, an idle CPU randomly selects another CPU to steal threads from, and the idle CPU attempts to dequeue a thread batch associated with the CPU from the shared ring buffer. Polling may be handled through the use of a shared poller array to dynamically distribute polling across multiple CPUs.