Patent classifications
G06F9/544
Data processing system with adjustable speed of processor and operating method thereof
A data processing system includes a controller configured to control data input/output for a memory according to a request of a host. The controller may include a buffer memory including a plurality of buffers configured to store data transmitted from the memory, a processor group including a plurality of cores respectively connected to the plurality of buffers, each core configured to read respective data from its respective buffer and perform computation using the read data, and a speed control component configured to adjust an operating speed of the processor group based on an amount of unread data of each buffer corresponding to each of the plurality of cores.
Zero copy socket splicing
Some embodiments provide a novel method for splicing Transmission Control Protocol (TCP) sockets on a computing device that processes a kernel of an operating system. The method receives a set of packets at a first TCP socket of the kernel. The method stores the set of packets at a kernel memory location sends the set of packets directly from the kernel memory location out through a second TCP socket of the kernel.
SYSTEM AND METHOD FOR DYNAMIC DATA PROTECTION ARCHITECTURE
A system for providing data protection services for data hosted by composed information handling systems includes a system includes a system control processor manager. The manager obtains a data protection architecture; identifies, based on the data protection architecture, first computing resources for a first pool that provides a first set of functionalities of the data protection services; identifies, based on the data protection architecture, second computing resources for a second pool that provides a second set of functionalities of the data protection services; assigns, based on hardware components of the first computing resources, a portion of the first set of functionalities to a first portion of the first computing resources; assigns, based on the hardware components of the first computing resources, a second portion of the first set of functionalities to a second portion of the first computing resources; and instantiates, based on the assignments, the data protection architecture.
Message Synchronization System
A method for synchronizing messages between processors is provided. The method comprising receiving, by a first external device, inbound messages for applications running redundantly in high integrity mode on two or more multi-core processors. The inbound messages are synchronously copied to the multi-core processors. The multi-core processors send outbound messages to respective alignment queues in the first external device or a second external device, wherein the outbound messages contain calculation results from the inbound messages. The first or second external device compares the alignment queues. Matched outbound messages in the alignment queues are sent to a network or data bus. Any unmatched outbound messages in the alignment queues are discarded.
Hierarchical sort/merge structure using a request pipe
A sort device includes a compare unit on one level of a hierarchical structure that includes a plurality of levels. The compare unit to compare one beat of one record with another beat of another record to provide a winner beat. The sort device further includes another compare unit on another level of the hierarchical structure to provide a further beat to the compare unit, and a request pipe to be used to request that the other compare unit provide the further beat to the compare unit.
Grouping requests to reduce inter-process communication in memory systems
A memory system having a set of media, a plurality of inter-process communication channels, and a controller configured to run a plurality of processes that communicate with each other using inter-process communication messages transmitted via the plurality of inter-process communication channels, in response to requests from a host system to store data in the media or retrieve data from the media. The memory system has a message manager that examines requests from the host system, identifies a plurality of combinable requests, generates a combined request, and provides the combined request to the plurality of processes as a substitute of the plurality of combinable requests.
System and method for maximizing processor and server use
A system and method for operating fewer servers near maximum capacity as opposed to operating more servers at low capacity is disclosed. Computational tasks are made as small as possible to be completed within the available capacity of the servers. Computational tasks that are similar may be distributed to the same computing node (including a processor) to improve RAM utilization. Additionally, workloads may be scheduled onto multicore processors to maximize the average number of processing cores utilized per clock cycle.
AVOIDANCE OF GARBAGE COLLECTION IN HIGH PERFORMANCE MEMORY MANAGEMENT SYSTEMS
Systems, apparatuses and methods may provide for technology that detects a creation of a thread, dedicates a memory region to objects associated with the thread, and conducts a reclamation of the memory region in response to a termination of the thread. In one example, the memory region is a heap region and the reclamation bypasses at least a pause phase and a copy phase of a garbage collection process with respect to the heap region.
HOST APPARATUS, HETEROGENEOUS SYSTEM ARCHITECTURE DEVICE, AND HETEROGENEOUS SYSTEM BASED ON UNIFIED VIRTUAL MEMORY
Disclosed herein is a heterogeneous system based on unified virtual memory. The heterogeneous system based on unified virtual memory may include a host for compiling a kernel program, which is source code of a user application, in a binary form and delivering the compiled kernel program to a heterogenous system architecture device, the heterogenous system architecture device for processing operation of the kernel program delivered from the host in parallel using two or more different types of processing elements, and unified virtual memory shared between the host and the heterogenous system architecture device.
One-sided reliable remote direct memory operations
Techniques are provided to allow more sophisticated operations to be performed remotely by machines that are not fully functional. Operations that can be performed reliably by a machine that has experienced a hardware and/or software error are referred to herein as Remote Direct Memory Operations or “RDMOs”. Unlike RDMAs, which typically involve trivially simple operations such as the retrieval of a single value from the memory of a remote machine, RDMOs may be arbitrarily complex. The techniques described herein can help applications run without interruption when there are software faults or glitches on a remote system with which they interact.