Systems and methods of error handling in a network interface card (NIC) are provided. For a data packet destined for a local virtual machine (VM), if the NIC cannot determine a valid translation memory address for a virtual memory address in a buffer descriptor from a receive queue of the VM, the NIC can retrieve a backup buffer descriptor from a hypervisor queue, and store the packet in a host memory location indicated by an address in the backup buffer descriptor. For a transmission request from a local VM, if the NIC cannot determine a valid translated address for a virtual memory address in the packet descriptor from a transmit queue of the VM, the NIC can send a message to a hypervisor backup queue, and generate and transmit a data packet based on data in a memory page reallocated by the hypervisor.

A storage device includes a nonvolatile memory device and a memory controller. After writing first data at the first page, the memory controller writes second data at a second page. The memory controller generates first check data corresponding to the first data and second check data corresponding to the second data. The memory controller recovers the first and second physical addresses and the first and second logical addresses based on the second check data.

Methods, apparatus, systems and articles of manufacture are disclosed to establish a data pipeline between cloud computing platforms. An apparatus includes a producer registration controller to register a data producer with a data pipeline service in a public cloud network, the data producer associated with a private cloud network, a consumer registration controller to register a data consumer with the data pipeline service, and a communication controller to, in response to the registration of the data consumer, transmit data generated by the public cloud network from the data consumer to the data buffer via a first data plane gateway, and, in response to a validation of the data consumer, transmit the data from the data buffer to the data consumer via a second data plane gateway, the first data plane gateway different from the second data plane gateway.

A system includes having buffers and a processing device that receives a read request with a logical block address (LBA) value for a memory device, creates a logical transfer unit (LTU) value, to include the LBA value, that is mapped to a first physical address of the memory device, and generates command tags that are to direct the processing device to retrieve data from the memory device and store the data in buffers. The command tags include a first command tag associated with the first physical address and a second command tag associated with a second physical address that sequentially follows the first physical address. The processor further creates an entry in the read cache table for the buffers. The entry can include a starting LBA value set to the first LBA value and the read offset value corresponding to the amount of data.

A streaming platform reader includes: a reader thread configured to retrieve messages from a plurality of partitions of a streaming platform, wherein each message in the plurality of partitions is associated with a unique identifier; a plurality of queues coupled to the reader thread configured to store messages or an end of partition signal from the reader thread, wherein each queue includes a first position that stores the earliest message stored by a queue; an extraction thread controlled by gate control logic that: compares the identifiers of all of the messages in the first positions of the queues of the plurality of queues, and forwards, to a pool of queues associated with a pool of processing threads, the message content of the message associated with the earliest identifier; and wherein the gate control logic blocks the extraction thread unless each of the queues contains a message or an end of partition signal.

A method for managing resources, a computing device, and a computer-readable storage medium are provided. The method includes obtaining device information of multiple physical devices included in a computing node to confirm physical devices supporting a predetermined hardware resource management method; initializing at least one physical device among the physical devices supporting the predetermined hardware resource management method as a unified device view device; allocating a virtual storage address of the unified device view device, where the virtual storage address is mapped to a physical storage address of the physical device participating in the unified device view; transmitting data to the virtual storage address of the unified device view device; and issuing a computing task to the unified device view device via a task queue for using the physical device participating in the unified device view to execute the computing task.

A computer system configured to enable communication between two or more virtual platforms is disclosed. The computer system comprises a physical processor configured to run the two or more virtual platforms. The computer system further comprises a memory. The memory comprises one or more separate memory portions allocated to each of the two or more virtual platforms, wherein within at least one memory portion allocated to one of the virtual platform a predefined range of addresses is configured as a shared device memory, the shared device memory being accessible by all the virtual platforms. Firmware running on a first virtual platform is configured to transfer a data packet from the first virtual platform to one or more further virtual platforms via the shared device memory.

Methods and devices for asset tracking are provided. An example method involves obtaining a stream of raw data, adding data points from the stream of raw data to a data buffer in a first cycle of data, performing a dataset simplification algorithm on the first cycle of data to determine whether one or more data points from the first cycle of data are to be recorded, preparing the data buffer for a second cycle of data, including determining a group of carry-over data points to be included in the second cycle of data, and continuing to add data points from the stream of raw data to the data buffer in the second cycle of data.

Various embodiments for a thread management system are described herein. An embodiment operates by determining that one or more scheduler threads of a server are allocated from a shared memory. A request to spawn a native thread at the server is received. The request is intercepted and an override for the request in which the resources for spawning the native thread are requested from the shared memory is executed. An allocation of resources for spawning and executing the native thread is received from the shared memory. An error on the server is detected. The shared memory is dumped into a dump file responsive to determining the error. The dump file includes an indication of what threads were allocated from the shared memory. The one or more scheduler threads and the native thread are restarted after the dumping.

Embodiments relate to a compiler. The compiler decreases data fetch and read associated with storing data in a data buffer of a neural processor circuit to or from a system memory. The data buffer can store an input slice of data for processing by a neural engine(s) of the neural processor circuit, an output slice of data output from the neural engine(s), and/or an intermediate data slice of data.