A system includes a memory including a ring buffer having a plurality of slots, a processor in communication with the memory, a guest operating system, and a hypervisor. The hypervisor is configured to detect a request associated with a memory entry, retrieve up to a predetermined quantity of memory entries in the ring buffer from an original slot to an end slot, and test a respective descriptor of each successive slot from the original slot through the end slot while the respective descriptor of each successive slot in the ring buffer remains unchanged. Additionally, the hypervisor is configured to execute the request associated with the memory entries and respective valid descriptors. The hypervisor is also configured to walk the ring buffer backwards from the end slot to the original slot while clearing the valid descriptors.

In one or more embodiments, one or more systems, one or more methods, and/or one or more methods may: register a subroutine configured to store multiple addresses of a volatile memory medium VMM of an information handling system (IHS); for each IHS initialization executable/OS executable pair of multiple IHS initialization executable/OS executable pairs: retrieve, from a first non-volatile memory medium (NVMM), an IHS initialization executable of the IHS initialization executable/OS executable pair; copy, by the IHS initialization executable, an OS executable of the IHS initialization executable/OS executable pair from the first NVMM to the VMM; call, by the IHS initialization executable, the subroutine; store, by the subroutine, an address associated with the OS executable via a data structure stored by the VMM; and copy, by a first OS executable, the OS executable from the VMM to a second NVMM based at least on the address associated with the OS executable.

Providing supplemental information to a guest operating system by a hypervisor is disclosed. A hypervisor executing on a host computing device initiates a virtual machine comprising a guest kernel. The hypervisor determines an address of a shared memory area that is accessible by the guest kernel and accessible by the hypervisor. The hypervisor determines that an event has occurred for which supplemental information exists, the event corresponding to a particular event code of a plurality of different event codes. The hypervisor determines a location in the shared memory area that corresponds to the particular event code. The hypervisor inserts the supplemental information at the location in the shared memory area. The hypervisor causes an interrupt of the guest kernel.

A method includes assessing an input in a buffer against a rule in a first node of a rule tree to determine that an action should be performed and updating the buffer with results of performing the action. The method also includes inserting an indication of the input, the rule, and the results of performing the action into a tracker log and passing the updated buffer to a second node in the rule tree in response to determining that the first node points to the second node.

Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a state of multiple intellectual property (IP) cores that have access to a common cache via a central fabric is observed. Responsive to the observed state being indicative of performance of a standalone workload by a first IP core of the multiple IP cores, the common cache is treated as a local cache of the first IP core by powering off the central fabric and causing the first IP core to access the common cache via a low power access path between the first IP core and the common cache that is outside of the central fabric.

Disclosed herein is a system, method, and computer program product for dynamically altering message rates through a transport. The system, method, and computer program product continually operates a transport and analyzes trend data using a moving average of producer rates and consumer rates. Keeping message flow at an optimal rate as system conditions vary throughout time enables efficient delivery of messages through multiple subsystems and intermediary transports to the messages' manifold endpoints.

Embodiments of this application disclose a fault detection method, and relate to the field of computer technologies. The method according to embodiments of this application includes: obtaining a scheduling table of a target task, where the scheduling table is used to indicate at least one test pattern, the at least one test pattern is used to detect a fault in a target logic circuit, and the target logic circuit is a logic circuit configured to execute the target task; and executing the at least one test pattern based on the scheduling table, to detect the fault in the target logic circuit. By determining the scheduling table of the target task, the test pattern included in the scheduling table is executed, so that execution of all test patterns in a software test library can be avoided. This reduces load of a processor, and effectively improves working efficiency of the processor.

A workflow engine tool is disclosed that enables scientists and engineers to programmatically author workflows (e.g., a directed acyclic graph, “DAG”) with nearly no overhead, using a simpler script that needs almost no modifications for portability among multiple different workflow engines. This permits users to focus on the business logic of the project, avoiding the distracting tedious overhead related to workflow management (such as uploading modules, drawing edges, setting parameters, and other tasks). The workflow engine tool provides an abstraction layer on top of workflow engines, introducing a binding function that converts a programming language function (e.g., a normal python function) into a workflow module definition. The workflow engine tool infers module instances and induces edge dependencies automatically by inferring from a programming language script to build a DAG.

Described herein are systems, methods, and software to generate user interfaces to indicate software-defined storage information in view of available hardware resources. In one example, a user interface service may obtain enclosure information associated with enclosures in a computing environment and may determine a storage overview for the plurality of enclosures based on the enclosure information. The user interface service may further determine a function for each storage device in the storage overview in relation to a software-defined storage configuration for the computing environment and generate a user interface to indicate the storage overview with the function for each storage device in the plurality of enclosures.

There are provided a controller and a memory system having the controller. The controller includes: a first storage area configured to store mapping information between logical addresses of logical regions of a storage device coupled to the controller and physical addresses of memory blocks of the storage device, the logical regions being divided into logical units including a first logical unit; and a second storage area configured to store allocation information on logical addresses of logical regions allocated to the first logical unit, each of the logical regions allocated to the first logical unit having a corresponding index, wherein the second storage area is further configured to store a location table for the first logical unit that includes index information having a smallest index corresponding to a logical region allocated to the first logical unit without having other indices corresponding to remaining logical regions allocated to the first logical unit and number information on a total number of the logical regions allocated to the first logical unit.