A multi-layer serverless sizing stack may determine a compute sizing correction for a serverless function. The serverless sizing stack may analyze historical data to determine a base compute allocation and compute buffer range. The serverless sizing stack may traverse the compute buffer range in an iterative analysis to determine a compute size for the serverless function to support efficient computational-operation when the serverless function is instantiated.

A motion control program that causes a computer to function as: a channel management unit on a real-time OS that creates an operation channel common to a plurality of reception units on a shared memory; the plurality of reception units on a non-real-time OS each of which instructs via the operation channel, when receiving a preparation instruction, a generation unit to generate a control command channel; the channel management unit that creates, on the shared memory, a control command channel associated with the user-created program that has provided the preparation instruction; the reception unit that receives a control command and stores control command information indicating a content of the received control command, in the control command channel; and a fixed-cycle processing unit that transmits an interpolation command to a control target device for each motion control cycle, based on the control command information obtained from the control command channel.

A network switch may include a database, a network analysis data producer having a first application program interface, a network analysis data consumer having a second application program interface and a shared memory accessible by the first application program interface and the second application program interface. The network analysis data producer is to store network analysis data on a region of the shared memory and store an index to the region in the database for retrieval by the network analysis data consumer.

A data processing system includes a host processor, a processor suitable for processing a task instructed by the host processor, a memory, shared by the host processor and the processor, that is suitable for storing data processed by the host processor and the processor, respectively, and a memory controller suitable for checking whether a stored data processed by the host processor and the processor are reused, and for sorting and managing the stored data as a first data and a second data based on the check result.

A system, method and program product for synchronizing client-based data with data in a shared resource. A system is provided that receives data from a plurality of client devices, the data being indicative of at least one action associated with a shared resource accessible by the plurality of client devices, and inserts a plurality of actions indicated by the data as nodes into a polytree queue, wherein actions that do not depend on other actions in the polytree queue are inserted as root level nodes, and actions that depend on other actions in the polytree queue are inserted as child nodes. The system further executes the nodes in the polytree queue to synchronize the data from the plurality of client devices with the shared resource, wherein root level nodes are scheduled for immediate concurrent execution, and execution of child nodes is delayed until parent nodes of an associated child node are executed.

Systems and methods for implementing a secure communication channel between kernel and user mode components are provided. According to an embodiment, a shared memory is provided through which a kernel mode process and a user mode process communicate. The kernel mode process is assigned read-write access to the shared memory. The user mode process is assigned read-only access to the shared memory. An offset-based linked list is implemented within the shared memory. Kernel-to-user messages are communicated from the kernel mode process to the user mode process by adding corresponding nodes to the offset-based linked list. One or more kernel-to-user messages are read by the user mode process following the offset-based linked list in order. The kernel mode process is signaled by the user mode process that a kernel-to-user message has been consumed by the user mode process through an input output control (ioctl) system call or an event object.

Systems and methods for processing memory address spaces corresponding to a shared memory are disclosed. After a writer restart process, pre-restart writer pointers of a pre-restart writer addressable space in the shared memory are replaced with corresponding location independent pointers. A writer pointer translation table is rebuilt in the shared memory to replace an association of modified pre-restart writer pointers and pre-restart translation base pointers based on the pre-restart writer pointers, respectively, with an association of modified post-restart writer pointers and post-restart translation base pointers based on post-restart writer pointers, respectively. After the writer pointer translation table is rebuilt, the location independent pointers are replaced with post-restart writer pointers in the shared memory, respectively, and the post-restart writer pointers are stored in the shared memory for access by one or more readers of the shared memory.

In one embodiment, a method includes creating, by a computing device, an inter process communication (IPC) channel for communication from a producer process to a consumer process. The IPC channel includes a message buffer mapped to a first virtual address space of a kernel of an operating system and to a second virtual address space of the consumer process in a user space of the operating system. A sender handle for the message buffer is sent to the producer process. The kernel receives a request, which includes the sender handle, to send a message from the producer process to the consumer process through the IPC channel. Responsive to a determination that the request is permitted, the kernel writes the message to the message buffer using the sender handle, such that message written in the message buffer is accessible to the consumer process through the second address space.

Examples described herein provide a method for reducing lane-to-lane serial skew in an integrated circuit. In an example using a processor-based system, a maximum clock skew is determined from clock skews of respective lanes of a transmitter of the IC. Each of the clock skews corresponds to a skew of a clock signal of the respective lane relative to a same reference clock signal. A skew match amount is determined for each lane of the lanes of the transmitter. The skew match amount for a respective lane of the lanes is based on the maximum clock skew and the clock skew of the respective lane. Configuration data is generated to configure the transmitter to shift incoming data for each lane of the lanes based on the skew match amount for the respective lane.

Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.