Method and apparatuses for communicating instruction data items from a control apparatus to a device to be controlled are disclosed. The control apparatus receives a request for at least one instruction data item from a device and responds the request by sending a response message. The responding comprises selectively including at least one instruction data item in the response message based at least partly on determination whether the requested at least one data item has been sent before.

Examples described herein include systems and methods for brokerless reliable totally ordered many-to-many inter-process communication on a single node. A messaging protocol is provided that utilizes shared memory for one of the control plane and data plane, and multicast for the other plane. Readers and writers can store either control messages or message data in the shared memory, including in a ring buffer. Write access to portions of the shared memory can be controlled by a robust futex, which includes a locking mechanism that is crash recoverable. In general, the writers and readers can control the pace of communications and the crash of any process does not crash the overall messaging on the node.

A baseboard management controller in an information handling system receives a human interface device input and converts the human interface device input into a human interface device scan code for storage at a human interface device descriptor buffer. The baseboard management controller determines whether or not the human interface device descriptor buffer is full and copying, when the human interface device descriptor buffer is full, the human interface scan codes in the human interface device descriptor buffer to a memory segment and sending an error code to a host system. The baseboard management controller also clears the human interface device descriptor buffer and re-populates the human interface device descriptor buffer with the human interface device scan code and the human interface device scan codes from the memory segment.

Devices and techniques for pipeline merging in a circuit are described herein. A parallel pipeline result can be obtained for a transaction index of a parallel pipeline. Here, the parallel pipeline is one of several parallel pipelines that share transaction indices. An element in a vector can be marked. The element corresponds to the transaction index. The vector is one of several vectors respectively assigned to the several parallel pipelines. Further each element in the several vectors corresponds to a possible transaction index with respective elements between vectors corresponding to the same transaction index. Elements between the several vectors that correspond to the same transaction index can be compared to determine when a transaction is complete. In response to the transaction being complete, the result can be released to an output buffer in response to the transaction being complete.

Devices and techniques for variable pipeline length in a barrel-multithreaded processor are described herein. A completion time for an instruction can be determined prior to insertion into a pipeline of a processor. A conflict between the instruction and a different instruction based on the completion time can be detected. Here, the different instruction is already in the pipeline and the conflict detected when the completion time equals the previously determined completion time for the different instruction. A difference between the completion time and an unconflicted completion time can then be calculated and completion of the instruction delayed by the difference.

Remote cache slots are donated in a storage array without requiring a cache slot starved compute node to search for candidates in remote portions of a shared memory. One or more donor compute nodes create donor cache slots that are reserved for donation. The cache slot starved compute node broadcasts a message to the donor compute nodes indicating a need for donor cache slots. The donor compute nodes provide donor cache slots to the cache slot starved compute node in response to the message. The message may be broadcast by updating a mask of compute node operational status in the shared memory. The donor cache slots may be provided by providing pointers to the donor cache slots.

An information handling system for compressing data includes multiple compression engines, a source data buffer to provide compression data to the compression engines, at least one destination data buffer to receive compressed data from the compression engines, and a compression engine driver. Each compression engine is configured to provide a different compression function. The compression engine driver directs each compression engine to compress data from the source data buffer, and retrieves select compressed data from a first one of the compression engines from the at least one destination data buffer. The selection is based upon a selection criterion.

An intrusion detection system, comprising a monitor to receive messages from a target over a low-latency communication link comprising a controlled access memory structure logically positioned between the target and the monitor using point-to-point interconnects, the controlled access memory structure to receive a message from the target indicating that the target has entered a controlled mode of operation.

Apparatuses, systems, and techniques to cause data to be selectively stored in one or more memory locations. In at least one embodiment, a processor is to cause data to be selectively stored in one or more memory locations based, at least in part, on one or more threads to use the data.

The invention provides a technology for suppressing a delay in communication between a plurality of cores that perform parallel processing. In the invention, an ECU 302 of a vehicle control system 2 includes a plurality of cores 401 and a shared memory 405. When transmitting data in the inter-core communication, a transmission side core 401-1 writes a counter value updated according to the data and a writing order to a buffer unit 901 which is determined by a counter value managed for each communication system, which is stored in each of the plurality of buffer units 901 provided in the shared memory 405. When receiving data in the inter-core communication, a reception side core 401-2 reads data from the buffer unit 901 in which the latest data for each communication system is stored, which is determined by the counter value stored in each of the plurality of buffer units 901.