In an embodiment, responsive to determining: (a) a first command is not of a particular command type associated with one or more hardware modules associated with a particular routing node, or (b) at least one argument used for executing the first command is not available: transmitting the first command to another routing node in the hardware routing mesh. Upon receiving a second command of the command bundle and determining: (a) the second command is of the particular command type associated with the hardware module(s), and (b) arguments used by the second command are available: transmitting the second command to the hardware module(s) associated with the particular routing node for execution by the hardware module(s). Thereafter, the command bundle is modified based on execution of the second command by at least refraining from transmitting the second command of the command bundle to any other routing nodes in the hardware routing mesh.

Embodiments of the present invention provide a computer system, a computer program product, and a method that comprises ingesting tabular data from at least one modality of a plurality of modalities; simultaneously extracting data and generating a prediction model for a task of a computing device from the extracted data from at least two modalities in the plurality of modalities; generating a data signature based on the generated prediction model from the at least two modalities by leveraging the generated prediction model for ingested tabular data and extracted data; comparing the generated data signature to identified data signatures stored in at least one modality in the plurality of modalities; and performing a task based on the generated data signature and a validation of the comparison of identified data signatures.

A data processing system including a shared memory; a host processor configured to possess an ownership of the shared memory, and process a first task by accessing the shared memory; a processor configured to possess the ownership transferred from the host processor, and process a second task by accessing the shared memory; and a memory controller coupled among the host processor, the processor, and the shared memory, and configured to allow the host processor or the processor to access the shared memory according to the ownership.

A communication architecture, for exchanging data between processing units that are intended to operate in parallel comprises a communication system comprising a set of interfaces each intended to be linked to a processing unit, a set of sequencers that are able to define, for each processing unit, time intervals of access to a shared memory accessible by the processing units for writing and reading data, for the sequential arbitration of accesses to said memory, and a set of address managers able to allocate each processing unit ports for access to the shared memory.

The present disclosure is related to performing speculation in, for example, a memory device or a computing system that includes a memory device. Speculation can be used to identify data that is accessed together or to predict data that will be accessed with greater frequency. The identified data can be organized to improve efficiency in providing access to the data.

Systems and methods for thread execution transition are disclosed. An example system includes a memory and a processor with first and second registers. An application and a supervisor are configured to execute on the processor, which suspends execution of a first thread executing the supervisor. One execution state of the first thread is stored in the first register. The application stores a request in a first shared memory location. The application executes on a second thread and another execution state of the second thread is stored in the second register. The processor suspends execution of the second thread and resumes execution of the first thread. The supervisor retrieves data for the request from the first shared memory location, and processes the data, including storing a result to a second shared memory location. The processor suspends execution of the first thread and resumes execution of the second thread.

A lens distortion correction function operates by backmapping output images to the uncorrected, distorted input images. As a vision image processor completes processing on the image data lines needed for the lens distortion correction function to operate on a group of output, undistorted image lines, the lens distortion correction function begins processing the image data. This improves image processing pipeline delays by overlapping the operations. The vision image processor provides output image data to a circular buffer in SRAM, rather than providing it to DRAM. The lens distortion correction function operates from the image data in the circular buffer. By operating from the SRAM circular buffer, access to the DRAM for the highly fragmented backmapping image data read operations is removed, improving available DRAM bandwidth. By using a circular buffer, less space is needed in the SRAM. The improved memory operations further improve the image processing pipeline delays.

An apparatus includes a processor to: use an identifier of a requesting device or operator thereof to identify federated area(s) to which access is authorized; based on data dependencies among a set of tasks of a job flow, derive an order of performance specifying the first task to be performed; store, within a task queue, a task routine execution request message including an identifier associated with the first task, and federated area identifier(s) of the identified federated area(s); within a resolver container, in response to storage of the task routine execution request message, use the identifier associated with the first task and identifier(s) of the federated area(s) to identify one in which a first task routine is stored; within a task container, execute the first task routine to perform the first task; and upon completion of the job flow, transmit an indication of completion to the requesting device.

Methods for providing simultaneous access to a hardware data stream to multiple applications are disclosed. The first application to access a hardware device is responsible for providing and publishing an application programming interface (API) that provides access to the hardware device's data stream, which other applications can then call to gain access to the data stream. In some examples, the first application may be a server process or daemon dedicated to managing the hardware device data stream and publishing the API. In some further examples, the first application may instead may carry out user functionality unrelated to managing the hardware device.

Techniques are disclosed to operate binary objects across private address spaces. In various embodiments, a private shared memory segment is allocated for two non-privileged address spaces, the first comprising a home address space and the second comprising a target address space. One or more executable modules are loaded in a private address space of the home address space. One or more program call routines and an environment to schedule system request blocks (SRB) are built in the home address space. The environment to schedule system request blocks is configured to be used to schedule an SRB into the target address space, the SRB comprising information configured to cause the target address space to cause an associated one of the executable modules to execute.