Patent classifications
G06F9/544
Compiling and scheduling transactions in neural network processor
Embodiments relate to a compiler. The compiler decreases data fetch and read associated with storing data in a data buffer of a neural processor circuit to or from a system memory. The data buffer can store an input slice of data for processing by a neural engine(s) of the neural processor circuit, an output slice of data output from the neural engine(s), and/or an intermediate data slice of data.
Information processing device, method, and program
A guest operating system (120) of a virtual machine (12) writes, into a shared memory (111), data destined for a virtual machine (13) together with a destination ID and a source ID. The delivery manager (181) supplies data to a communicator (182) when a determination is made that an information processing device (21) is specified in a delivery information table (161) as a delivery destination corresponding to the destination ID and the source ID. The communicator (182) transmits the data supplied from the delivery manager (181) to the information processing device. The delivery manager (181) writes first data into a shared memory (112) and delivers the first data to the virtual machine (13) when determining that a delivery destination corresponding to the destination ID and the source ID is not specified in the deliver information table (161).
Programmatic container monitoring
A computer-implemented method of monitoring programmatic containers (containers) through executing a computer program in a kernel space is disclosed. The method comprises storing trace data in a memory buffer that is shared by the kernel space and a user space, the trace data being related to execution of a process associated with a container at an execution point of the process. The method also comprises retrieving container data related to the container through raw access of one or more kernel data structures when execution of the process is stopped. In addition, the method comprises storing the container data in association with the trace data in the memory buffer.
Method and apparatus for memory allocation in a multi-core processor system, and recording medium therefor
According to the disclosure, a memory allocation method and device and recording medium in a multi-core processor system are disclosed. According to an embodiment, a method for allocating a shared variable to a memory in a multi-core processor system comprises mapping each task to a core, allocating unshared variables to memories times of access, to which are sequentially minimized, in descending order of actual variable access count, calculating an actual variable access count per core, selecting a core with a highest actual variable access count, and allocating a shared variable to a memory of the selected core.
MACHINE LEARNING OUTPUT SAMPLING FOR A DATA INTAKE AND QUERY SYSTEM
Systems and methods are described for providing a user interface through which a user can program operation of a data processing pipeline by specifying a graph of nodes that transform data and interconnections that designate routing of data between individual nodes within the graph. In response to a user request, a preview mode can be activated that causes the data processing pipeline to retrieve data from at least one source specified by the graph, transform the data according to the nodes of the graph, sample the transformed data, and display the sampling of the transformed data to at least one node without writing the transformed data to at least one destination specified by the graph.
Computing device compatible encryption and decryption
A method and apparatus encrypting data for use by an application includes receiving a first clear data in a security application running concurrently with the application. The security application encrypts the first clear data to generate a first encrypted package and distributes the encrypted package for use by the application or by other applications running concurrently with the application. The security application also receives and decrypts encrypted packages from the application or one of the other applications to provide clear data for use by the application. The security application may be implemented as a data entry utility that can be accessed directly by the application.
Hardware coherence for memory controller
A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.
Barrierless and fenceless shared memory synchronization with write flag toggling
When communicating through shared memory, a producer thread generates a value that is written to a location in a shared memory. The value is read from the shared memory by a consumer thread. The challenge is to ensure that the consumer thread reads the location only after the value is written and is thereby synchronized. When a memory location is written by a producer thread, a flag that is simultaneously stored in the memory location along with the value is toggled. The consumer thread tracks information to determine whether the flag stored in the location indicates whether the producer has written the value to the location. The flag is read and written simultaneously with reading and writing the location in memory, thereby eliminating the need for a memory fence. After all of the consumer threads read the value, the location may be reused to write additional value(s) and simultaneously toggle the flag.
Online machine learning algorithm for a data intake and query system
Systems and methods are described for processing ingested data using an online machine learning algorithm as the data is being ingested. For example, the online machine learning algorithm can be an adaptive thresholding algorithm used to identify outliers in a moving window of data. As another example, the online machine learning algorithm can be a sequential outlier detector that detects anomalous sequences of logs or events. As another example, the online machine learning algorithm can be a sentiment analyzer that determines whether text has a positive, negative, or neutral sentiment. As another example, the online machine learning algorithm can be a drift detector that detects whether ingested data marks the start of a change in the distribution of a time-series.
Swappable online machine learning algorithms implemented in a data intake and query system
Systems and methods are described for testing one or more machine learning algorithms in parallel with an existing machine learning algorithm implemented within a data processing pipeline. Each machine learning algorithm can train a machine learning model that receives a live stream of raw machine data. The output of the machine learning model trained by the existing machine learning algorithm may be written to an external storage system, but the output of the machine learning model(s) trained by the test machine learning algorithm(s) may not be written to an external storage system. After some time, performance of the test machine learning algorithm(s) and the existing machine learning algorithm is evaluated. If the test machine learning algorithm performs better than the existing machine learning algorithm, then the machine learning algorithms can be swapped without any downtime and without needed to re-train a machine learning model using previously seen raw machine data.