Patent classifications
G06F9/544
CACHING IDENTIFIERS FOR ACCESS COMMANDS
Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.
Variable pipeline length in a barrel-multithreaded processor
Devices and techniques for variable pipeline length in a barrel-multithreaded processor are described herein. A completion time for an instruction can be determined prior to insertion into a pipeline of a processor. A conflict between the instruction and a different instruction based on the completion time can be detected. Here, the different instruction is already in the pipeline and the conflict detected when the completion time equals the previously determined completion time for the different instruction. A difference between the completion time and an unconflicted completion time can then be calculated and completion of the instruction delayed by the difference.
Discovering graymail through real-time analysis of incoming email
Techniques for identifying and processing graymail are disclosed. An electronic message store is accessed. A determination is made that a first message included in the electronic message store represents graymail, including by accessing a profile associated with an addressee of the first message. A remedial action is taken in response to determining that the first message represents graymail.
Parallel matrix multiplication technique optimized for memory fetches
A matrix multiplication circuit comprises a memory storage device, processing circuitry, a parallel multiply circuit, and buffer circuits. The parallel multiply circuit simultaneously performs a count of multiplies in a parallel multiplication operation. The buffer circuits include prefetch buffer circuits each having a storage array dimension corresponding to the count of multiplies in the parallel multiplication operation. The processing circuitry loads a first prefetch buffer circuit with values from the first matrix; fetches a value of the second matrix and, in parallel with the fetch, preload the second prefetch buffer circuit with another value from the first matrix; initiates a parallel multiply of the fetched value of the second matrix and the values in the first prefetch buffer circuit; and stores partial product results of the parallel multiply, including adding a current partial product result to a previously stored partial product result.
Auto termination of applications based on application and user activity
A system and method that automatically terminates an application. A method includes monitoring activity data points for an application launched by a client device within a workspace environment. The activity data points may include user interactions with a physical interface component. State data for each file associated with the application is monitored and, if a determination is made that the application is inactive based on the activity data points, the method determines if a file associated with the application includes unsaved content based on state data. If it is determined that no files for the application include unsaved content, the method forecasts whether the application will be inactive for a future period based on the activity data. The application is terminated if it is determined that no files for the application include unsaved content and the application is forecast to be inactive.
Extrema-retentive data buffering and simplification
Methods and devices for asset tracking are provided. An example method involves obtaining a stream of raw data, adding data points from the stream of raw data to a data buffer in a first cycle of data, performing a dataset simplification algorithm on the first cycle of data to determine whether one or more data points from the first cycle of data are to be recorded, preparing the data buffer for a second cycle of data, including determining a group of carry-over data points to be included in the second cycle of data, and continuing to add data points from the stream of raw data to the data buffer in the second cycle of data.
ENABLING SCREEN-SHARE IN ONLINE MEETING PLATFORM BASED ON VIRTUAL DESKTOP
A method comprises: at a computer device configured with user applications grouped in multiple virtual desktops hosted on and displayed by the computer device: establishing an online meeting with remote computer devices over a network; responsive to user input, selecting one of the multiple virtual desktops to be a shared virtual desktop, such that all other ones of the multiple virtual desktops become unshared virtual desktops; sharing, with the remote computer devices, the shared virtual desktop, including first user applications of the user applications that are grouped in the shared virtual desktop; and not sharing, with the remote computer devices, any of the unshared virtual desktops and second user applications of the user applications that are grouped in the unshared virtual desktops.
Separate IO and control threads on one datapath Pod of a RIC
To provide a low latency near RT RIC, some embodiments separate the RIC's functions into several different components that operate on different machines (e.g., execute on VMs or Pods) operating on the same host computer or different host computers. Some embodiments also provide high speed interfaces between these machines. Some or all of these interfaces operate in non-blocking, lockless manner in order to ensure that critical near RT RIC operations (e.g., datapath processes) are not delayed due to multiple requests causing one or more components to stall. In addition, each of these RIC components also has an internal architecture that is designed to operate in a non-blocking manner so that no one process of a component can block the operation of another process of the component. All of these low latency features allow the near RT RIC to serve as a high speed IO between the E2 nodes and the xApps.
SYSTEMS AND METHODS FOR LIMITING OPERATIONS ON DOCUMENTS AT AN EXTERNAL SYSTEM
Responsive to an indication to lock an item managed by a content server, the content server locks the item at the content server and locks a copy of the item managed by an external system to prevent editing of the copy of the item. The external system operates in a cloud computing environment. The content server updates a user-interface (UI) to indicate that the item is locked from editing.
NETWORK SWITCH WITH ENDPOINT AND DIRECT MEMORY ACCESS CONTROLLERS FOR IN-VEHICLE DATA TRANSFERS
A network switch includes a data bus, a register, an endpoint controller and a direct memory access controller. The endpoint controller is configured to receive a descriptor generated by a device driver of a host system, store the descriptor in the register, and transfer data between a root complex controller of the host system and the data bus. The descriptor identifies an address of a buffer in a memory of the host system. The direct memory access controller is configured to receive the address of the buffer from the endpoint controller or the register and, based on the address and an indication generated by the device driver, independently control transfer of the data between the memory of the host system and a network device connected to the network switch. The direct memory access controller is a receive direct memory access controller or a transmit direct memory access controller.