A method for synchronous ingestion of input content may include determining, from an ingestion request, applicable ingestion pipeline components and an order by which the ingestion pipeline components are to be applied to input content; applying the ingestion pipeline components to the input content in the order determined from the ingestion request; updating a metadata file as the input content is processed by the ingestion pipeline components; and returning processed content, the metadata file, or both to a client device. The method may further include determining whether the ingestion request specifies a computing facility such as an indexer or a database downstream from the ingestion pipeline. If so, a processing result may be communicated to the computing facility for further processing. A server system may implement synchronous ingestion, asynchronous ingestion, or both.

A storage device includes a nonvolatile memory device and a memory controller. After writing first data at the first page, the memory controller writes second data at a second page. The memory controller generates first check data corresponding to the first data and second check data corresponding to the second data. The memory controller recovers the first and second physical addresses and the first and second logical addresses based on the second check data.

An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.

A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions. The method further includes, in response to an indication that the pipeline does not contain any pending blocking transactions, preventing new snoop transactions from entering the pipeline while permitting new response transactions and victim transactions to enter the pipeline; in response to an indication that the pipeline does not contain any pending snoop transactions, preventing, all new transactions from entering the pipeline; and, in response to an indication that the pipeline does not contain any pending transactions, performing the global operation on the L2 cache.

Techniques are provided to allow more sophisticated operations to be performed remotely by machines that are not fully functional. Operations that can be performed reliably by a machine that has experienced a hardware and/or software error are referred to herein as Remote Direct Memory Operations or “RDMOs”. Unlike RDMAs, which typically involve trivially simple operations such as the retrieval of a single value from the memory of a remote machine, RDMOs may be arbitrarily complex. The techniques described herein can help applications run without interruption when there are software faults or glitches on a remote system with which they interact.

A method for a shared-memory-based SVM to provide high availability of service is disclosed. In an embodiment, an agent process of the SVM receives a signal that one or more data packets have been queued in a shared memory device of one or more shared memory devices. Upon receiving the signal, the agent process determines whether the SVM has been designated as active for the shared memory device, and if it has, the agent process reads the one or more data packets from the shared memory device. As the data packets are read from the shared memory device: for each data packet, of the one or more data packets read from the shared memory device: the agent process determines whether an indication that the packet is to be transmitted to its destination is received, and if the indication is received, the packet is placed back to the shared memory device.

A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.

A control apparatus where control programs and information programs coexist is allowed to change programs flexibly. The control programs and information programs are installed in the control apparatus, which is provided with a shared area. The shared area is an area that at least one control program and at least one information program can access. Shared information is stored in the shared area. The shared information includes at least one of information related to an I/O port accessed by the control programs, and information related to the control program. Each control program is a program that performs scan operation of outputting control information on the relevant control object apparatus coupled to the I/O port accessed for controlling a control object apparatus with respect to the control program, to this I/O port. Each information program is a program that performs information processing that does not include the scan operation.

Methods and apparatus for correcting out-of-order data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a peripheral-side processor receives data from an external device and stores it to memory. The host processor writes data structures (transfer descriptors) describing the received data, regardless of the order the data was received from the external device. The transfer descriptors are written to a memory structure (transfer descriptor ring) in memory shared between the host and peripheral processors. The peripheral reads the transfer descriptors and writes data structures (completion descriptors) to another memory structure (completion descriptor ring). The completion descriptors are written to enable the host processor to retrieve the stored data in the correct order. In optimized variants, a completion descriptor describes groups of transfer descriptors. In some variants, the peripheral processor caches the transfer descriptors to offload them from the transfer descriptor ring.

Systems and methods for implementing a secure communication channel between kernel and user mode components are provided. According to an embodiment, a shared memory is provided through which a kernel mode process and a user mode process communicate. The kernel mode process is assigned read-write access to the shared memory. The user mode process is assigned read-only access to the shared memory. An offset-based linked list is implemented within the shared memory. Kernel-to-user messages are communicated from the kernel mode process to the user mode process by adding corresponding nodes to the offset-based linked list. One or more kernel-to-user messages are read by the user mode process following the offset-based linked list in order. The kernel mode process is signaled by the user mode process that a kernel-to-user message has been consumed by the user mode process through an input output control (ioctl) system call or an event object.