A first processing unit such as a graphics processing unit (GPU) pipelines that execute commands and a scheduler to schedule one or more first commands for execution by one or more of the pipelines. The one or more first commands are received from a user mode driver in a second processing unit such as a central processing unit (CPU). The scheduler schedules one or more second commands for execution in response to completing execution of the one or more first commands and without notifying the second processing unit. In some cases, the first processing unit includes a direct memory access (DMA) engine that writes blocks of information from the first processing unit to a memory. The one or more second commands program the DMA engine to write a block of information including results generated by executing the one or more first commands.

A method includes creating a publisher configured to send messages over a channel having a shared memory. The method includes creating at least one subscriber configured to receive the messages over the channel by sequentially referencing memory slots of the plurality of memory slots. The method includes determining that the next sequential memory slot is currently referenced by a subscriber. The method includes delaying sending the message by the publisher based on determining that the next sequential memory slot is currently referenced by the subscriber. The method includes receiving an event trigger indicative of message reading by the subscriber. The method includes, responsive to receiving the event trigger, determining that the next sequential memory slot is not currently referenced. The method includes sending the message to the next sequential memory slot based on determining that the next sequential memory slot is not currently referenced.

Apparatuses, systems, and techniques to interface with an accelerator. In at least one embodiment, an application provides workloads to a logical device, and the logical device distributes the workloads across a plurality of accelerators.

In some examples, a storage medium to stores information indicating address locations of virtual serial ports, where the virtual serial ports are associated with respective virtual machines (VMs). A controller that is separate from a hypervisor is to detect, based on the information, an access of a first virtual serial port associated with a first VM of the plurality of VMs, and communicate data between the first VM and another entity through the first virtual serial port.

Examples herein describe techniques for transferring data between data processing engines in an array using shared memory. In one embodiment, certain engines in the array have connections to the memory in neighboring engines. For example, each engine may have its own assigned memory module which can be accessed directly (e.g., without using a streaming or memory mapped interconnect). In addition, the surrounding engines (referred to herein as the neighboring engines) may also include direct connections to the memory module. Using these direct connections, the cores can load and/or store data in the neighboring memory modules.

The present disclosure relates to a method for inter-process communication, a related computing device and storage medium. The method comprises: receiving, by a first process, a request for a storage space of a first size; requesting, by the first process, a first number of shared memory blocks from an operating system, wherein the storage space of each shared memory block is not smaller than the first size; in response to the operating system allocating the first number of shared memory blocks, adding, by the first process, the first number of first nodes in a first linked list, wherein each of the first nodes corresponds to a respective one of the allocated shared memory blocks; and sending, by the first process, identifiers associated with the allocated shared memory blocks to a second process.

An information processing apparatus includes: a video acquisition unit configured to acquire imaging data from an imaging unit in response to processing of a first application; a first video processing unit configured to store the imaging data acquired by the video acquisition unit in a shared memory so as to be usable by processing of a second application other than the first application; and a second video processing unit configured to acquire the imaging data from the shared memory at a time interval corresponding to the second application and transmit the imaging data to the second application.

To provide a low latency near RT RIC, some embodiments separate the RIC's functions into several different components that operate on different machines (e.g., execute on VMs or Pods) operating on the same host computer or different host computers. Some embodiments also provide high speed interfaces between these machines. Some or all of these interfaces operate in non-blocking, lockless manner in order to ensure that critical near RT RIC operations (e.g., datapath processes) are not delayed due to multiple requests causing one or more components to stall. In addition, each of these RIC components also has an internal architecture that is designed to operate in a non-blocking manner so that no one process of a component can block the operation of another process of the component. All of these low latency features allow the near RT RIC to serve as a high speed IO between the E2 nodes and the xApps.

Some embodiments provide various methods for offloading operations in an O-RAN (Open Radio Access Network) onto control plane (CP) or edge applications that execute on host computers with hardware accelerators in software defined datacenters (SDDCs). At the CP or edge application operating on a machine executing on a host computer with a hardware accelerator, the method of some embodiments receives data, from an O-RAN E2 unit, to perform an operation. The method uses a driver of the machine to communicate directly with the hardware accelerator to direct the hardware accelerator to perform a set of computations associated with the operation. This driver allows the communication with the hardware accelerator to bypass an intervening set of drivers executing on the host computer between the machine's driver and the hardware accelerator. Through this driver, the application in some embodiments receives the computation results, which it then provides to one or more O-RAN components (e.g., to the E2 unit that provided the data, another E2 unit or another control plane or edge application).

Some embodiments provide various methods for offloading operations in an O-RAN (Open Radio Access Network) onto control plane (CP) or edge applications that execute on host computers with hardware accelerators in software defined datacenters (SDDCs). At the CP or edge application operating on a machine executing on a host computer with a hardware accelerator, the method of some embodiments receives data, from an O-RAN E2 unit, to perform an operation. The method uses a driver of the machine to communicate directly with the hardware accelerator to direct the hardware accelerator to perform a set of computations associated with the operation. This driver allows the communication with the hardware accelerator to bypass an intervening set of drivers executing on the host computer between the machine's driver and the hardware accelerator. Through this driver, the application in some embodiments receives the computation results, which it then provides to one or more O-RAN components (e.g., to the E2 unit that provided the data, another E2 unit or another control plane or edge application).