A motion control program that causes a computer to function as: a reception unit on a non-real-time OS that receives a control command that controls a plurality of control target devices, and notifies a control unit of control command information indicating a content of the received control command; the control unit that generates an interpolation command for each of the control target devices repeatedly for each of motion control cycles based on the control command information notified from the reception unit, and stores the generated interpolation command; and a communication module unit that obtains an interpolation command, converts the obtained interpolation command from a predetermined signal format which can be recognized by the control unit into a signal format with a communication interface standard which can be recognized by each of the plurality of control target devices, and transmits the interpolation command.

A system comprising a gateway for interfacing external data sources with one or more accelerators. The gateway comprises a plurality of virtual gateways, each of which is configured to stream data from the external data sources to one or more associated accelerators. The plurality of virtual gateways are each configured to stream data from external data sources so that the data is received at an associated accelerator in response to a synchronisation point being obtained by a synchronisation zone. Each of the virtual gateways is assigned a virtual ID so that when data is received at the gateway, data can be delivered to the appropriate gateway.

A parallel-processing computer system is provided for parallel processing of data packets conveyed in a communication network. The system comprises: a memory; a plurality of processing elements; and a program stored at the memory for execution by the plurality of processing elements. The at least one program comprises instructions for: receiving one or more data packets comprising operational instructions from an application; establishing a pipeline element for carrying out a service process, which comprises a plurality of sub-pipelines, each associated with a respective task required for carrying out the service process and wherein each of the plurality of processing elements is operative for carrying out tasks associated with a respective sub-pipeline belonging to the plurality of sub-pipelines; and executing simultaneously by the plurality of processing elements, tasks associated with the plurality of sub-pipelines, wherein the plurality of processing elements is implementing a parallel processing of each data packet.

A computing device may include a memory and a processor cooperating with the memory to generate data to correct errors in transmission of packets to a client device based upon a ratio of a first bandwidth in which to transfer content of a buffer and a second bandwidth in which to transfer the generated data, the packets to transfer the content and the generated data to the client device via a channel. The processor may further adjust the ratio based upon a parameter of the channel, and send the content of the buffer and the generated data via packets and through the channel to the client device based on the adjusted ratio.

A system and method for providing security of sensitive information within chips using SIMD micro-architecture are described. A command processor within a parallel data processing unit, such as a graphics processing unit (GPU), schedules commands across multiple compute units based on state information. When the command processor determines a rescheduling condition is satisfied, it causes the overwriting of at least a portion of data stored in each of the one or more local memories used by the multiple compute units. The command processor also stores in the secure memory a copy of state information associated with a given group of commands and later checks it to ensure corruption by a malicious or careless program is prevented.

A universal floating-point Instruction Set Architecture (ISA) implemented entirely in hardware. Using a single instruction, the universal floating-point ISA has the ability, in hardware, to compute directly with dual decimal character sequences up to IEEE 754-2008 “H=20” in length, without first having to explicitly perform a conversion-to-binary-format process in software before computing with these human-readable floating-point or integer representations. The ISA does not employ opcodes, but rather pushes and pulls “gobs” of data without the encumbering opcode fetch, decode, and execute bottleneck. Instead, the ISA employs stand-alone, memory-mapped operators, complete with their own pipeline that is completely decoupled from the processor's primary push-pull pipeline. The ISA employs special three-port, 1024-bit wide SRAMS; a special dual asymmetric system stack; memory-mapped stand-alone hardware operators with private result buffers having simultaneously readable side-A and side-B read ports; and dual hardware H=20 convertFromDecimalCharacter conversion operators.

Techniques perform data storage. Such techniques may involve writing metadata to a first cache of a first processor, the metadata indicating allocation of a storage resource to user data. Such techniques may further involve determining an address range of the metadata in the first cache. Such techniques may further involve copying only data stored in the address range in the first cache to a second cache of a second processor. Accordingly, the data transmission volume between two processors is reduced, which helps to improve the overall performance of a storage system.

Various approaches for memory encryption management within an edge computing system are described. In an edge computing system deployment, a computing device includes capabilities to store and manage encrypted data in memory, through processing circuitry configured to: allocate memory encryption keys according to a data isolation policy for a microservice domain, with respective keys used for encryption of respective sets of data within the memory (e.g., among different tenants or tenant groups); and, share data associated with a first microservice to a second microservice of the domain. Such sharing may be based on the communication of an encryption key, used to encrypt the data in memory, from a proxy (such as a sidecar) associated with the first microservice to a proxy associated with the second microservice; and maintaining the encrypted data within the memory, for use with the second microservice, as accessible with the communicated encryption key.

A system for atomically transferring vectors of data from a transmitter of the vectors of data to a receiver of the vectors of data may include a plurality of memory buffers configured to store the vectors of the data, each buffer configured to store one vector of the vectors of data at a time, the plurality of memory buffers comprising at least three memory buffers and a controller for controlling the plurality of memory buffers. The controller may be configured to, responsive to a condition for transferring information represented by the vectors of data to the receiver, determine which of the plurality of buffers from which the receiver may receive most-recently updated information completely written to the plurality of buffers by the transmitter. The controller may further be configured to, responsive to a condition for updating information represented by the vectors of data, determine which of the plurality of buffers for the transmitter to write updated information without blocking atomic receipt by the receiver of information from a most-recently updated buffer.

In one or more embodiments, one or more systems, one or more methods, and/or one or more methods may: register a subroutine configured to store multiple addresses of a volatile memory medium VMM of an information handling system (IHS); for each IHS initialization executable/OS executable pair of multiple IHS initialization executable/OS executable pairs: retrieve, from a first non-volatile memory medium (NVMM), an IHS initialization executable of the IHS initialization executable/OS executable pair; copy, by the IHS initialization executable, an OS executable of the IHS initialization executable/OS executable pair from the first NVMM to the VMM; call, by the IHS initialization executable, the subroutine; store, by the subroutine, an address associated with the OS executable via a data structure stored by the VMM; and copy, by a first OS executable, the OS executable from the VMM to a second NVMM based at least on the address associated with the OS executable.