Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

A system for monitoring job execution includes an interface and a processor. The interface is configured to receive an indication to start a cluster processing job. The processor is configured to determine whether processing a data instance associated with the cluster processing job satisfies a watchdog criterion; and in the event that processing the data instance satisfies the watchdog criterion, cause the processing of the data instance to be killed.

Embodiments for reducing panic shutdown of components in a pipelined data processing system. Components are monitored for health, processing progress, and dependencies during normal system operation. A directed graph is generated showing non-circular dependencies of components in the pipeline. Deadlock of a particular component may or may not signal a panic condition depending on whether any of its presently downstream and depended on components are operating properly. The continuously monitored knowledge of proper operation of all downstream components is thus used to intelligently apply or defer panic alerts to keep the system operating uninterrupted from panic conditions that might soon or eventually be fixed by continued operation of the system pipeline.

Dynamic logging includes generating parsed event data by at least one natural language processor responsive to event data of a log for transactions of a target application. In response to the parsed event data, a first classifier classifies context states of the respective transactions of the target application. In response, a second classifier classifies trouble prone states of the respective transactions, wherein the trouble prone states are for respective hierarchical levels. When a logic module determines, for a current one of the trouble prone states for a current transaction, that the current trouble prone state is a higher trouble prone level than for a transaction immediately preceding the current transaction, the logic module sends an increased log detail selection to the target application, so that a greater amount of log detail is logged for at least a next transaction after the current transaction.

An apparatus comprises a processing device configured to identify, at a first microservice, a service call that is to be transmitted to a second microservice, and to modify the service call to include context information, the context information characterizing a current state of execution of one or more tasks by one of the first microservice and the second microservice. The processing device is further configured to provide, from the first microservice to the second microservice, the modified service call including the context information. The context information enables re-initiation of said one of the first microservice and the second microservice to continue execution of the one or more tasks from the current state.

The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.

In an information processing apparatus, a control unit receives operation instructions. Each time receiving an operation instruction, the control unit detects the number of operating circuits that are to operate in accordance with the received operation instruction, in a circuit group of circuits that operate in synchronization with a clock signal. In addition, each time receiving an operation instruction, the control unit determines whether power supply noise that is likely to cause a timing error in the circuit group will occur, on the basis of a result of comparing an increase in the number of operating circuits per prescribed time period with a threshold, and lowers the frequency of the clock signal when determining that the power supply noise will occur.

Systems, methods, and other embodiments associated with patching database objects while a database system is online are described. In one embodiment, a patch command is defined and identifies a database code object, wherein the patch command is configured to modify code of the database code object. A serialized lock is requested from the database system for the database code object, wherein the serialized lock prohibits executing applications of the database system from accessing the database code object. In response to receiving the serialized lock from the database system, the code of the database code object is modified with a patch code to generate a modified database code object. The modified database code object is compiled and the serialized lock on the database code object is released to allow other executing applications to call and access the database code object.

A computer-implemented method for capturing system memory dumps includes receiving, by a diagnostic data component, an instruction to capture a system memory dump associated with a computer process being executed by a computing system comprising one or more processing units, the system memory dump comprising data from a plurality of memory locations associated with the computer process. In response to determining that the system memory dump satisfies a predetermined criterion, the diagnostic data component sends a request for a computing resource boost from the computing system. Further, in response to the request for the computing resource boost being granted, the diagnostic data component uses additional computing resources from the one or more processing units to store the data from the plurality of memory locations in the system memory dump and executing the backlogged operations that were halted due to the system memory dump capture.

An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes a first processor for executing a custom BMC firmware stack, and transmitting a watchdog message at an ongoing basis. The BMC also includes a second processor for receiving the watchdog message. When the watchdog message is received within a specified elapsed period of time, allow continued operation of the custom BMC firmware stack, and when not received within the specified elapsed period of time, place the BMC in a failsafe mode of operation.