A storage system includes a plurality of controllers and a relay device and is configured to perform mirror transfer between the plurality of controllers, the relay device detects an abnormality in each device located between the plurality of controller and aggregates error information in a register, and a first controller module that is a source of performing the mirror transfer among the plurality of controllers reads content of the register and determines whether the mirror transfer is completed normally, after the mirror transfer is performed.

This application discloses a storage system, a data processing method, an apparatus, a node, and a storage medium, and pertains to the field of data storage technologies. In the method, a client determines an address that is in a storage unit and that is used to store to-be-written data, and sends the to-be-written data to a first storage device that is in a storage node and that is corresponding to the storage unit, so that the first storage device stores the to-be-written data while a CPU of the storage node does not need to determine a hard disk LBA corresponding to virtual address space, and a hard disk does not need to determine a corresponding physical address based on the hard disk LBA.

A data storage device includes a memory device having a plurality of blocks and a controller coupled to the memory device. The controller is configured to determine that an uncorrectable error correction code (UECC) failure has occurred to a block of the plurality of blocks, enable a UECC anti-strike mechanism, and erase the block. The UECC anti-strike mechanism comprises converting a read failure associated with the block to an erase failure. The controller is further configured to retire the block upon determining that the erase is unsuccessful.

A memory device can dynamically select a voltage step size for programming (i.e., charging) memory cells. The memory device can increase the voltage step size to reduce programming time or decrease the voltage step size to reduce errors. The memory device can identify device conditions, such as temperature or amount of use (e.g., a count of program/erase cycles). The memory device can increase the voltage step size when the device conditions are less likely to cause errors (e.g., in a middle temperature range or below a threshold number of program/erase cycles) or can decrease the voltage step size when the device conditions are more likely to cause errors (e.g., in a high or low temperature range or above a threshold number of program/erase cycles).

Managing storage systems that are synchronously replicating a dataset, including: detecting a change in membership to the set of storage systems synchronously replicating the dataset; and applying one or more membership protocols to determine a new set of storage systems to synchronously replicate the dataset, wherein the one or more membership protocols include a quorum protocol, an external management protocol, or a racing protocol, and wherein one or more I/O operations directed to the dataset are applied to a new set of storage systems.

Various implementations described herein relate to systems and methods for predicting and managing drive hazards for Solid State Drive (SSD) devices in a data center, including receiving telemetry data corresponding to SSDs, determining future hazard of one of those SSDs based on an a-priori model or machine learning, and causing migration of data from that SSD to another SSD.

Devices and techniques for fatal error logging in a memory device are described herein. For example, a read request can be received for a component of the memory device. A fatal error indication of an error that prevents correct execution of read request can be detected. Diagnostic information for the failure indication can be collected. A response to the read request can then be made with a portion of the diagnostic information as payload instead of the user data that would have occupied the payload had the read succeeded. Metadata in the response can be used to communicate an error code.

Systems and methods for adaptive fault prediction analysis are described. In one embodiment, the system includes one or more computing components, and one or more hardware controllers. In some embodiments, the storage system includes a storage drive. At least one of the one or more hardware controllers is configured to analyze one or more tolerance limits of a first computing component among the plurality of computing components; calculate a failure metric of the first computing component based at least in part on the analysis of the one or more tolerance limits of the first computing component; analyze sensor data from the first computing component in real time; and update the failure metric based at least in part on the analyzing of the sensor data.

One embodiment provides a computer implemented method of for monitoring and upgrading a dual-flash device. The method includes performing an OS upgrade on a server; writing an upgraded OS to the dual-flash device; updating a grub.cfg file corresponding to the upgraded OS; and deleting old OS files from the dual-flash device.

A processing device in a memory system determines to send system state information associated with the memory device to a host system and identifies a subset of a plurality of event entries from a staging buffer based on one or more filtering factors, the plurality of event entries corresponding to events associated with the memory device. The processing device further sends the subset of the plurality of event entries as the system state information to the host system over a communication pipe having limited bandwidth.