A failure bit count (FBC) circuit for memory array is provided. The memory array includes pages each having plural sectors and a redundancy column. The FBC circuit includes FBC units, in which each FBC unit is respectively coupled to each sector for providing a failure bit count current; a redundancy FBC unit coupled to the redundancy column and provides a redundancy current; a switch having a first end and a second end capable of being switched to couple to one of outputs of the FBC units to receive the failure bit count current from one of the FBC units; a comparator having a first input end that receives a reference current, and a second input end that receives a measurement current obtained by adding the failure measurement current and the redundancy current, and an output end outputting a judge signal to indicate a number of failure bits for each sector.

A memory controller includes an interface and a processor. The interface communicates with memory cells that store data in predefined Programming Voltages (PVs). The processor is configured to produce observation samples that each includes (i) a target sample read from a target memory cell in a target Word Line (WL), and (ii) neighbor samples read from neighbor memory cells. Based on the observation samples, the processor is further configured to jointly estimate Cross-Coupling Coefficients (CCFs), by searching for CCFs that aim to minimize a predefined function of distances calculated between transformed observation samples that have been transformed using the CCFs and combinations of PVs that are closest to the respective transformed observation samples, to apply, based on the CCFs, cross-coupling cancelation to readout samples retrieved from the memory cells to produce enhanced readout samples, and to perform a storage operation related to reading data, using the enhanced readout samples.

Disclosed herein are a method for generating Gaussian error data using flash memory and an apparatus using the method. The method includes receiving a request to generate Gaussian error data and delivering an operation command to flash memory; generating Gaussian error noise based on a threshold voltage that is generated when the flash memory performs the operation command; and generating Gaussian error data so as to correspond to the Gaussian error noise and providing the same.

Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, identifying, by the processing device, a plurality of partitions located on a die of the memory device. The operations performed by the processing device further include selecting, based on evaluating a predefined criterion reflecting a physical layout of the die of the memory device, a first partition and a second partition of the plurality of partitions. The operations performed by the processing device further include generating a codeword comprising first data residing on the first partition and second data residing on the second partition.

Staging data on a storage element integrating fast durable storage and bulk durable storage, including: receiving, at a storage element integrating fast durable storage and bulk durable storage, a data storage operation from a host computer; storing data corresponding to the data storage operation within fast durable storage in accordance with a first data resiliency technique; and responsive to detecting a condition for transferring data between fast durable storage and bulk durable storage, transferring the data from fast durable storage to bulk durable storage in accordance with a second data resiliency technique.

A method of operating a storage device includes sensing a standby current flowing through the storage device, determining based on the sensed standby current and at least one reference value whether a product abnormality has occurred within the storage device, and when it is determined the product abnormality has occurred, performing a step-wise control operation in which two or more control processes associated with an operation of the storage device are sequentially executed.

An approach to identifying a corrective action for a data storage device (DSD), such as one implemented in a fleet of DSDs in a data center, involves receiving error data about excursions from normal operational behavior of the DSD, inputting data representing a particular excursion into a probabilistic decision network which characterizes a set of DSD operational metrics and certain DSD controller rules that represent internal controls of the DSD and corresponding conditional relationships among the operational metrics, determining from the decision network the likelihood that one or more possible causes was a contributing factor to the particular excursion, and determining a corrective action for the particular excursion based on the determined likelihood of a particular cause of the one or more possible causes. The corrective action may then be shared with the DSD for in-situ execution of corresponding self-repair operations.

A technique for correcting errors in a data storage system operates while the data storage system remains online. The technique includes identifying an object for validation, scanning a plurality of pointers, and counting a number of pointers that point to the object. The technique further includes repairing a discrepancy between the count of pointers and a reference count stored in connection with the object.

One or more computing devices, systems, and/or methods for classifier validation are provided. A set of in-sample examples are partitioned into a reduced in-sample set and a remaining in-sample set. The reduced in-sample set is processed using a set of classifiers. A subset of classifiers are identified as having error counts, over the reduced in-sample set, below a threshold number of errors. A training procedure is executed to select a classifier having a minimum error rate over the set of in-sample examples. If the classifier is within the subset of classifiers, then an out-of-sample error bound is determined for the classifier.

The present disclosure includes apparatuses and methods for proactive corrective actions in memory based on a probabilistic data structure. A number of embodiments include a memory, and circuitry configured to input information associated with a subset of data stored in the memory into a probabilistic data structure and proactively determine, at least partially using the probabilistic data structure, whether to take a corrective action on the subset of data stored in the memory.