A semiconductor memory apparatus may include: a memory cell array; an ECC (Error Check and Correction) circuit configured to detect an error from data read from the memory cell array in response to a read command, correct the detected error, and output an error correction signal whenever an error is corrected; and an EF (Error Flag) generator configured to enter a flag output mode when the number of times that the error correction signal is generated during a monitoring period reaches a threshold, and output the error correction signal as an error flag in the flag output mode.

A memory circuit includes a first memory array and a second memory array. The first memory array and the second memory array are independent. The first memory array includes a plurality of general bits and the second memory array includes a plurality of spare bits. An address of defective bit in the first memory array is stored in the second memory array, and the memory circuit repairs the defective bit by one of the spare bits according to the address.

A system includes a memory circuitry configured to generate multiple results, each result using a different read voltage, in response to one or each received data access command. The multiple read results may be used to dynamically calibrate a read voltage assigned to generate a read result in response to a read command.

A memory system may include a memory device including a first memory block group and a second memory block group; and a memory controller configured to designate a first memory block of memory blocks included in the first memory block group as an open block and designate a second memory block of memory blocks included in the second memory block group as the open block, and perform a program operation on the first and second memory blocks designated as the open blocks. When the first memory block designated as the open block is changed to a closed block, the memory controller may determine whether to designate a third memory block among the memory blocks included in the first or the second memory block group as a new open block based on a number of times voltage abnormalities have occurred on a voltage supplied to the memory device.

The present disclosure provides a content addressable memory (CAM) for repairing firmware of multi-plane read operations in a flash memory device. The CAM comprises a set of CAM registers configured to store a mapping table. The mapping table comprises a plurality of old addresses, each old address corresponding to a new address. The CAM also comprises N comparators coupling to the set of CAM registers, and configured to compare the old addresses with N input signals for performing the multi-plane read operations on N memory planes, wherein N is an integer greater than 1. The CAM further comprises N multiplexers coupling to the N comparators respectively and to the set of CAM registers, and configured to generate N output signals for the multi-plane read operations. At least one of the N output signals comprises the new address according to the mapping table and a comparison output by the comparators.

A first error rate based on a first read operation performed on a memory device is obtained. An individual data unit of the memory device that satisfies a first threshold criterion associated with a defect candidate is determined. A defect verification operation on the individual data unit to obtain a second error rate is performed. The individual data unit that satisfies a second threshold criterion associated with a defect is determined.

The present disclosure refers to apparatuses and methods for initializing electronic devices. An electronic device according to various embodiments includes a memory, and a processor operatively connected to the memory. The processor is configured to record, in the memory, software binaries received from an external device during a download mode. The processor is further configured to, when the download mode has ended, perform booting in a normal mode using a bootloader based on a determination indicating that a predetermined software binary is present among the software binaries recorded in the memory, and perform booting in a recovery mode using the bootloader based on the determination indicating that the predetermined software binary is absent from among the software binaries recorded in the memory.

A method includes obtaining a first memory log, where the first memory log includes log information of a plurality of garbage collections, and log information of each garbage collection includes a garbage collection time, and includes at least one of a downtime, memory usage after garbage collection, and memory usage before garbage collection, obtaining, based on log information in a first detection time window, first statistical information corresponding to the first detection time window, and determining, based on the first statistical information corresponding to the first detection time window, an anomaly degree corresponding to the log information in the first detection time window.

Virtual memory address space is divided according to areas of the virtual memory address and allocating some areas to low-cost volatile memory (such as RAM) when the memory areas are not required by an application to be stored in non-volatile memory, such as NVDIMM. A loader mechanism creates and maintains a layout address table in non-volatile memory for recovery from an unexpected reset.

Methods, apparatuses, and systems related to a memory device are described. A controller may be configured to predict a temperature of a memory based on a real-time temperature of the controller. Based on the predicted temperature of the memory, the controller may execute a remedial action to reduce an actual temperature of the memory for executing an upcoming operation.