Methods, systems, and devices for command block management are described. A memory device may receive a command (e.g., from a host device). The memory device may determine whether the command is defined by determining if the command is included within a set of defined commands. In the case that a received command is absent from the set of defined commands (e.g., the command is undefined), the memory device may block the command from being decoded for execution by the memory device. In some cases, the memory device may switch from a first operation mode to a second operation mode based on receiving an undefined command. The second operation mode may restrict an operation of the memory device, while the first mode may be less restrictive, in some cases. Additionally or alternatively, the memory device may indicate the undefined command to another device (e.g., the host device).

A controller of a non-volatile, dual, in-line memory modules (NVDIMM). A NVDIMM is configured to predict thermal events associated with save and restore operations prior to starting the save or restore operation. The controller of the NVDIMM includes a thermal event prediction circuit to predict whether a thermal event will occur in response to a request to perform a save or restore operation, and to cause the controller to perform an action in response to a determination that a thermal event is likely to occur. To predict the thermal event, the controller may be configured to predict a peak temperature of the save or restore operation based on a predicted temperature increase from an initial or starting temperature. The predicted temperature increase may be based on a rate of temperature change during the save or restore operation and a duration of the save or restore operation.

A method is described that includes processing, by a memory subsystem, a read memory command that is addressed to a first die of a memory device. The memory subsystem determines whether processing the read memory command failed to correctly read user data from the first die and, in response to determining that processing the read memory command failed to correctly read user data from the first die, determines whether the first die has failed. In response to determining that the first die has failed, the memory subsystem performs an abbreviated error recovery procedure to successfully perform the read memory command instead of a full error recovery procedure.

A controller for use in a memory device includes an error information generator configured to receive error information about an error occurring while a command is being processed at a protocol layer, generate command error information corresponding to the command based on the received error information, and store the generated command error information in a first storage area, and an error information manager configured to store the command error information, stored in the first storage area, in a second storage area in response to an external request.

Embodiments can include a scan of data associated with programmed memory cells is performed. The scan of data results in a bit error count (BEC) histogram. A trigger margin is determined from the BEC histogram. The determined trigger margin and a target trigger margin are compared. In response to the determined trigger margin being different than the target trigger margin, one or more program step characteristics is adjusted to adjust the determined trigger margin toward the target trigger margin.

One or more parameters indicative of a request to segment the memory device into multiple partitions for use by a host system are received. Responsive to receiving the one or more parameters indicative of the request to segment the memory device into multiple partitions, a first partition is configured with one or more configuration settings based on the one or more parameters. Configuring the first partition includes determining a memory type from multiple memory types based on the one or more parameters, and configuring the first partition to operate as the determined memory type. The memory types define a number of bits that a memory cell of the first partition is to store.

A system may include a graphics processing unit (GPU) and a processor. The GPU may include a GPU core and non-error-detection-and-correction (non-EDAC) graphics memory. The graphics memory may contain a data object and a copy of the data object. The processor may be configured to: instruct the GPU to handle the data object and the copy of the data object as textures; and instruct the GPU to execute a texture comparison shader program. The GPU core may be configured to: execute the texture comparison shader program; compare the data object and the copy of the data object; generate comparison results; and output the comparison results as pixels to an off-screen area of a framebuffer. The processor may further be configured to: obtain (a) a hash value of the off-screen area, or (b) the off-screen area; and determine whether the comparison results are at least one expected value.

A cache flush request is received in a first phase of a persistent memory flush flow, where the first phase is initiated by a host processor, and the cache flush request requests that data in cache memory be flushed to persistent memory within a system. A cache flush response is sent in the first phase responsive to the cache flush request, where the cache flush response identifies whether an error is detected in the first phase. A memory buffer flush request is received in a second phase of the persistent memory flush flow, where the second phase is initiated by the host processor upon completion of the first phase, and the memory buffer flush request requests that data in buffers of persistent memory devices in the system be flushed to persistent memory. A memory buffer flush response is sent in the second phase responsive to the memory buffer flush response.

An apparatus comprises a plurality of redundant processing units to perform data processing redundantly in lockstep; common mode fault detection circuitry to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory shared between the plurality of redundant processing units; and memory checking circuitry to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry indicating that the event indicative of a potential common mode fault has been detected.

An apparatus includes circuitry configured to generate multiple results, each result using a different read voltage, in response to one or each received data access command. The multiple read results may be used to dynamically calibrate a read voltage assigned to generate a read result in response to a read command.