A method includes holding a definition of multiple software-implemented tests for testing one or more hardware units of an Integrated Circuit (IC), and of invocation conditions that specify whether the tests are permitted to run. The tests are applied to the hardware units at least partially in parallel, using a processor in the IC, by repeatedly tracking respective execution states of the tests and evaluating the invocation conditions, and invoking a test that currently does not run but is permitted to run in accordance with the invocation conditions.

The invention relates to a method for automatically determining necessary or sufficient cause of a malfunction of a system made up of a plurality of hardware or software components. The method comprises, from the obtaining (22) of an execution trace including a sequence of events observed during the execution of the system, obtaining a tested subset of components comprising at least one component in which the execution trace has (24) at least one non-conformity with the specification of correct operation of said component and a subset of components processed in accordance with said tested subset of components; for a processed subset of components, a calculation, for each of the components of the system, of a prefix of an execution trace not affected by events that do not conform with the specification observed for the components of the processed subset of components, the determination of a counterfactual execution model of the processed subset making it possible to generate all of the possible behaviours, starting with the unaffected prefixes, in the absence of a malfunction of the components of the processed subset of components and the determination (28, 30) of the necessary or sufficient cause of the components of the subset of components tested for the malfunction of the system in accordance with the verification that said counterfactual model of the processed subset of components complies with said global property of the system.

An apparatus for controlling an inverter includes a volatile, first storage part; a nonvolatile, second storage part; and a control part configured to store data related to the status of the inverter in the first storage part when the inverter is driven and configured to select some of the data stored in the first storage part depending on the type of failure event when a failure event occurs and store the selected data in the second storage part.

Disclosed is a battery management unit. The battery management unit according to the present disclosure can prevent performance of an erroneous control algorithm by executing an infinite loop when an error occurs on a communication line.

A programmable logic controller includes an error detection unit, a data memory storing error occurrence information indicating, for each error kind, whether the error detection unit has detected an error, an error automatic cancellation processing unit determining whether an error factor of each error has been eliminated and, when the error factor has been eliminated, performing an error cancellation process including a process to change the error occurrence information to error non-occurrence, and an error-automatic-cancellation-permission determination unit referring to an error automatic cancellation permission setting and determining, when the error detection unit detects an error, whether the error is canceled by the error automatic cancellation processing unit on the basis of the error automatic cancellation permission setting, wherein the error automatic cancellation processing unit performs the error cancellation process on the error that the error-automatic-cancellation-permission determination unit has determined that the error automatic cancellation processing unit is to cancel.

The invention concerns a system on a chip (100) comprising a set of master modules which includes a main processing module (101a) and a direct memory access controller (DMA) (102a) associated with said module (101a), and at least one secondary processing module (101b) and a DMA (102b) associated with said module (101b), and slave modules; each master module being configured for connection to a clock source, a power supply, and slave modules which include a set of proximity peripherals (105a,b), at least one internal memory (104a,b) and a set (106) of peripherals and external memories shared by the master modules; said clock source, power supply, proximity peripherals (105a,b) and a cache memory (103a,b) of a master processing module and its DMA being dedicated to said master processing module and not shared with the other processing modules of the set of master modules; and said at least one internal memory (104a,b) of each master processing module and its DMA being dedicated to said master processing module, said main processing module (101a) being nevertheless able to access same.

Various systems, mediums, and methods may involve data engines configured to generate results associated with one or more entities based on neural network configurations. An exemplary system includes a data engine with a training module, a working module, an incremental training module, and a neural network. The data engine may process data associated with the one or more entities and transfer the processed data to an input layer of the neural network. Further, outputs from the input layer may be transferred to a hidden layer of the neural network. Yet further, outputs from the hidden layer may be transferred to an output layer of the neural network. As such, one or more results may be generated from an output layer of the neural network. The one or more results may include an assessment score of the one or more entities.

To provide a machining program processing apparatus capable of preventing an increase in the program correction time or does not let the program correction time go to waste. A machining program processing apparatus includes: a grammar checking unit executing grammar check of a machining program; a transmission processing unit transmitting the machining program to an external device; and a deletion processing unit deleting the machining program, wherein, when a transmission request of the machining program including a grammar error is received, the transmission processing unit confirms whether the transmission is to be permitted or not.

A data processing method for safe Instrumentation and Control Systems (I&C Systems) based on data processing in safety I&C Systems consisting of self-diagnosable modules of the platform with the unified architecture, to use specifically developed computing facilities implemented in FPGA, to design and configure the modules with the unified architecture of the unified units, to use units operation in different clock domains and diversity technologies, to design and configure the computing facilities, to provide mutual diagnostics and self-diagnostics for hardware, computing facilities, interfaces and data transfer at both modular and system levels implemented by hardware design tools and module platform logic, to use different software for application diverse logic design, to provide I&C System functional safety, to simplify design of modules and I&C Systems, to provide unified process and diagnostics and self-diagnostics coverage, to simplify user operation, to simplify I&C System maintenance and support.

Methods, devices, and systems for fault propagation in a building automation system are described herein. One device includes a memory, and a processor configured to execute executable instructions stored in the memory to receive an input associated with a fault occurring in the building automation system, execute a fault propagation of the fault using fault rules for the building automation system and causality relationships in a building information model associated with the building automation system, and generate, using the fault propagation of the fault, a fault output with respect to the building automation system.