Patent classifications
G06F11/0745
TRANSACTION EXCHANGE PLATFORM WITH A MESSENGER MICROSERVICE TO UPDATE TRANSACTIONS
Aspects described herein may relate to a transaction exchange platform using a streaming data platform (SDP) and microservices to process transactions according to review and approval workflows. The transaction exchange platform may receive transactions from origination sources, which may be added to the SDP as transaction objects. Microservices on the transaction exchange platform may interact with the transaction objects based on configured workflows associated with the transactions. Processing on the transaction exchange platform may facilitate clearing and settlement of transactions. Some aspects may provide for pausing the processing of transactions during a workflow. Other aspects may provide for a messaging microservice that permits communications between the transaction exchange platform and external third-parties.
TRANSACTION EXCHANGE PLATFORM WITH A WATCHDOG MICROSERVICE TO HANDLE STALLED TRANSACTIONS
Aspects described herein may relate to a transaction exchange platform using a streaming data platform (SDP) and microservices to process transactions according to review and approval workflows. The transaction exchange platform may receive transactions from origination sources, which may be added to the SDP as transaction objects. Microservices on the transaction exchange platform may interact with the transaction objects based on configured workflows associated with the transactions. Processing on the transaction exchange platform may facilitate clearing and settlement of transactions. Some aspects may provide for pausing the processing of transactions during a workflow. Other aspects may provide for a messaging microservice that permits communications between the transaction exchange platform and external third-parties.
Method and apparatus for disconnecting link between PCIe device and host
A method, an apparatus and a system for disconnecting a link between a Peripheral Component Interconnect Express (PCIe) device and a host, and pertains to the field of computer technologies. The PCIe device includes an endpoint (EP) device. The method includes: obtaining, by the EP device, an error type of an error in transmitting a transaction layer packet (TLP) between the PCIe device and the host; if the error type is a correctable error type specified in the PCIe protocol, collecting, by the EP device, statistics of a duration for which the error type exists; and disconnecting, by the EP device, a link between the PCIe device and the host if the statistics of the duration reaches a preset duration.
Autonomous transmit error detection of serial communication link receiver-transmitter and microcontroller system peripherals implementing the same
A serial communication link receiver-transmitter with autonomous transmission error detection is described, and a communication peripherals including the same. Transmit data at a transmitter and transmitted data output by the transmitter and received by the receiver are observed by an error detector configured to generate an error indication in response to difference between the transmit data and corresponding observed transmit data of a transmitted data frame. If a difference is detected a transmit error indicator is asserted.
SYSTEMS AND METHODS FOR DETECTING INTRA-CHIP COMMUNICATION ERRORS IN A RECONFIGURABLE HARDWARE SYSTEM
Systems and methods for error detection for an address channel are disclosed. The method includes generating a token, applying the token to a request at a source, and generating a first result. The request with the first result is transmitted to a destination over the address channel. A determination is made, at the destination, whether an error associated with the request has occurred. The determining whether the error has occurred includes: receiving a received request corresponding to the request over the address channel; receiving the first result with the received request; applying the token to the received request and generating a second result; comparing the first result with the second result; and transmitting a signal in response to the comparing.
Error detection within an integrated circuit chip
A method of performing error detection within an integrated circuit chip analyses transactions communicated over interconnect circuitry of the integrated circuit chip to detect whether a message contains a data error. A memory of the integrated circuit chip coupled to the interconnect circuitry is scanned to detect whether there is a data error stored in the memory, and in response to detecting a data error in a transaction communicated over the interconnect circuitry and/or a data error stored in the memory, a dedicated action indicative of a data error is performed.
TRANSACTION EXCHANGE PLATFORM WITH A VALIDATION MICROSERVICE FOR VALIDATING TRANSACTIONS BEFORE BEING PROCESSED
Aspects described herein may relate to a transaction exchange platform using a streaming data platform (SDP) and microservices to process transactions according to review and approval workflows. The transaction exchange platform may receive transactions from origination sources, which may be added to the SDP as transaction objects. As the transactions are received, the transactions may be analyzed to detect duplicate transactions and/or errors in the transactions. The transaction exchange platform may take steps to remediate transactions that are recognized as duplicates or predicted to generate one or more errors. Similarly, the transaction exchange platform may take steps to remediate transactions that are rejected by a clearinghouse.
Detecting and recovering from fatal storage errors
The present disclosure relates to systems, methods, and computer readable media for identifying and responding to a panic condition on a storage system on a computing node. For example, systems disclosed herein may include establishing recovery instructions between a host system and a storage system in responding to a future instance of a panic condition. The storage system may provide an indication of a self-detected panic condition in a variety of ways. In response to identifying the panic condition, the host system may perform one or more recovery actions in accordance with recovery instructions accessible to the host system. This may include performing resets of specific components and reinitializing communication between the host system and storage system in less invasive ways than slower and more expensive conventional approaches for responding to panic conditions on computing nodes.
Control method for error handling in a controller, storage medium therefor, controller and storage device
A control method for error handling in a controller, storage medium therefor, controller, and storage device. The controller for use in a first device is capable of linking to a second device according to an interconnection protocol. The control method includes the following steps: handling a first error information by transmitting a negative acknowledgement control (NAC) message to the second device according to the interconnection protocol through the controller, wherein the first error information indicates a first error occurring while the controller performs data reception according to a protocol layer of the interconnection protocol; and setting error handling status data to indicate that error handling is asserted for the first error information so that the controller does not handle sequence number errors occurring after the first error until the error handling status data is set to indicate that the error handling is de-asserted.
RETRIEVING DIAGNOSTIC INFORMATION FROM A PCI EXPRESS ENDPOINT
The present disclosure relates to systems, methods, and computer-readable media for facilitating efficient retrieval of diagnostic information from a computing endpoint that experiences a failure condition. For example, systems described herein may detect or otherwise identify a failure condition associating with the computing endpoint operating in an erroneous or unpredictable matter. Systems described herein may involve carving out a portion of memory on the computing endpoint that is accessible to a host system (e.g., a CPU). Systems described herein may further provide a discoverable resource that enables a host system to identify and collect the diagnostic data in response to identifying a failure condition in an efficient manner and without requiring that the computing endpoint be capable of responding to data requests.