This disclosure relates generally to a method and system for prediction of correct discrete sensor data, thus enabling continuous flow of data even when a discrete sensor fails. The activities of humans/subjects, housed in a smart environment is continuously monitored by plurality of non-intrusive discrete sensors embedded in living infrastructure. The collected discrete sensor data is usually sparse and largely unbalanced, wherein most of the discrete sensor data is ‘No’ and comparatively only a few samples of ‘Yes’, hence making prediction very challenging. The proposed prediction techniques based on introduction of temporal uncertainty is performed in several stages which includes pre-processing of received discrete sensor data, introduction of temporal uncertainty techniques followed by prediction based on neural network techniques of learning pattern using historical data.

Systems, methods, and apparatuses of creating a repair token for a distributed ledger are provided. A method includes identifying an error in the distributed ledger, the error associated with a first block on the distributed ledger, creating a repair token including content of the first block and a correction to the error, digitally signing and timestamping the repair token, and publishing the repair token to a repair token ledger.

Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.

In an embodiment, an apparatus includes a receiver circuit to: in response to a determination that the receiver circuit is in a high latency processing mode, transmit a hint signal to a transmitter circuit; receive a response message from the transmitter circuit; process the response message to reduce a current workload of the receiver circuit; and switch the receiver circuit from the high latency processing mode to a low latency processing mode. Other embodiments are described and claimed.

Techniques are described for providing a guaranteed commit outcome for global transactions that are optimized by deferring the commit processing to a resource manager, such as a DBMS, using optimizations. The “Distributed Transaction Processing: The XA Specification” standard specification is ambiguous regarding commit outcomes for transactions managed by DBMS, resulting in wrong results for vendors implementing the standard. The techniques described provide a guaranteed commit outcome when using the optimizations, creating the opportunity for safe replay of global transactions when a communication error or timeout occurs between the transaction manager and the resource manager, and eliminating ambiguous transaction outcomes reaching applications and end users.

Techniques described herein distinguished between global transactions in a session managed by a transaction manager, and those in the same session that are managed by the resource manager using the optimizations. The techniques provide a guaranteed commit outcome when the commit is managed by the resource manager, or when a transaction manager is managing the transaction. Switching between the different techniques to provide a guaranteed outcome occurs in a safe, performing, and silent manner, based on who controls the current transaction in a session. The solution includes one-phase processing, read only optimizations, and promotable transactions.

This disclosure pertains to systems and methods that allow users to specifically detect and correct errors within workflows quickly, efficiently, and with minimal repercussions. Once the error is corrected, users have the option to continue the workflow from the point of failure or from a point prior to the point of failure, while also having the option to bypass completed actions and/or other actions in a workflow. The improved communication technology comprises functionality that pauses relevant workflows or processes as soon as the error is detected and while it is corrected. The disclosure also improves communication technology between the networks and servers of separate parties relevant and/or dependent on successful execution of other workflows or processes; allowing for effective understanding, implementation, and engagement of business processes across organizational boundaries.

A control system is disclosed, including a first control device, a second control device and a driver component for driving signals on a data bus. The first control device includes a data output which is connected to a data input of the driver component, and a monitoring device for deactivating the data output in the event of a fault. A deactivation signal of the second control device for the driver component is fed to a data input of the first control device, and the first control device is configured to deactivate the data output in the event of an error signal at the data input.

A method obtains at least part of a file from a dispersed storage network (DSN) memory, and stores it in a data object cache. When the file is changed, a determination is made about where to store the changed file portions: in the data object cache or in the DSN. The changed file portions, for example a new copy of the part of the file obtained from the DSN, are encoded utilizing an error coding dispersal storage function, and stored in either the data object cache, or in the DSN memory.

A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.

An apparatus includes at least one processing device comprising a processor coupled to a memory, with the processing device being configured to maintain at least first and second journals for respective first and second different types of input-output requests, to move one or more entries between the first journal and the second journal under one or more specified conditions, to perform a clean-up operation for at least one of the first and second journals in conjunction with the moving of the one or more entries, and responsive to a failure occurring during the clean-up operation, to execute a contention resolution algorithm to resolve logical address range lock contentions between different entries of the first and second journals. The processing device illustratively comprises a storage controller of a storage system. The storage system may be, for example, a source storage system configured to carry out a synchronous replication process with a target storage system.