Patent classifications
G06F11/0754
ANOMALY DETECTION OF FIRMWARE REVISIONS IN A NETWORK
This disclosure describes systems, methods, and devices related to anomaly detection of CPE firmware revisions. A method may include collecting metrics data for a plurality of customer-provided equipment (CPE) models over a window of time; training a first autoencoder for a first CPE model of the plurality of CPE models using at least a portion of the metrics data to detect anomalies within a plurality of firmware versions of the first CPE model; identifying, using the first autoencoder, that a first firmware version of the plurality of firmware versions is anomalous across a first time series; and storing data indicating that the first firmware version of the plurality of firmware versions is anomalous across the first time series. Metrics data may include one or more of interactive voice response (IVR) session data; calls handled data; and truck schedule data.
Position-measuring device and method for operating the same
A position-measuring device includes a graduation carrier having a measuring graduation, position measurement electronics, a data memory and a power supply. The data memory includes a first memory which is a volatile memory for storing additional data, a second memory which is a writable non-volatile memory, and a memory controller for controlling transfer and storage of additional data from the first into the second memory. The power supply includes an input stage, a first output stage for the position measurement electronics, a second output stage for the data memory, and a voltage monitor which will turn off the first output stage of the power supply in response to a drop below a minimum value and signal the drop to the memory controller by a backup signal. In response to the backup signal, the memory controller will transfer additional data from the first memory into the second memory.
METHOD, ELECTRONIC DEVICE, AND COMPUTER PROGRAM PRODUCT FOR DATA PROCESSING
Embodiments of the present disclosure provide a method, an electronic device, and a computer program product for data processing. The method described herein includes determining identification information for an operation, wherein the identification information includes at least one field indicating content of the operation and a field indicating a unique identification of the operation. The method further includes identifying, based on the identification information, log entries for the operation in log files for at least one microservice invoked by the operation. The method further includes determining a log for the operation, wherein the log includes the identified log entries. With the solution for data processing of the present application, it is possible to easily acquire logs for an operation using identification information that includes a field indicating the content of the operation, so as to facilitate targeted analysis of the operation based on the content of the operation.
Methods for restricting read access to supply chips
An example method for restricting read access to content in the component circuitry and securing data in the supply item is disclosed. The method identifies the status of a read command, and depending upon whether the status disabled or enabled, either blocks the accessing of encrypted data stored in the supply chip, or allows the accessing of the encrypted data stored in the supply chip.
Memory system including a plurality of memory blocks
A memory system may include a memory device including a first memory block group and a second memory block group; and a memory controller configured to designate a first memory block of memory blocks included in the first memory block group as an open block and designate a second memory block of memory blocks included in the second memory block group as the open block, and perform a program operation on the first and second memory blocks designated as the open blocks. When the first memory block designated as the open block is changed to a closed block, the memory controller may determine whether to designate a third memory block among the memory blocks included in the first or the second memory block group as a new open block based on a number of times voltage abnormalities have occurred on a voltage supplied to the memory device.
SYSTEMS AND METHODS FOR FAULT DETECTION AND REPORTING THROUGH SERIAL INTERFACE TRANSCEIVERS
Circuitry, systems, and methods for fault detection and reporting comprise a fault detection circuit configured to detect one or more fault conditions that cause a state change in a fault pin voltage representative of a transceiver failure. Once the state of the fault pin voltage changes, a transceiver input generates a fault detection code. In embodiments, in response to the transceiver input receiving a first signal, the fault detection code is shifted to a transceiver output that may communicate the fault detection code to a controller. Once the transceiver input receives a second signal, the fault pin voltage may be reset to clear the fault detection code before resuming operations, including detecting additional fault conditions as they arise.
MACHINE LEARNING METHODS AND SYSTEMS FOR DISCOVERING PROBLEM INCIDENTS IN A DISTRIBUTED COMPUTER SYSTEM
Methods and systems are directed to discovering problem incidents in a distributed computing system. Events corresponding to historical problems incidents for the distributed computing system are retrieved from a data base. Sets of representative events of the various historical problem incidents for the distributed computing system are determined. A runtime problem incident in the distributed computing system is characterized by runtime events. The runtime problem incident is classified as corresponding to a historical problem incident of the historical problem incidents based on the runtime events and the sets of representative events. Remedial measures used to correct the historical problem incident may be used to correct the runtime problem.
Memory device and operating method of the same
A memory device includes a memory cell array including memory cells connected to word lines and bit lines. Each of the memory cells includes a switch element and a memory element, and has a first state or a second state in which a threshold voltage is within a first voltage range or a second voltage range, lower than the first voltage range. A memory controller is configured to execute a first read operation for the memory cells using a first read voltage, higher than a median value of the first voltage range, program first defect memory cells turned off during the first read operation to the first state, execute a second read operation for the memory cells using a second read voltage, lower than a median value of the second voltage range, and execute a repair operation for second defect memory cells turned on during the second read operation.
System and method for detecting anomalies by discovering sequences in log entries
A method for detecting an anomaly includes retrieving a log file that includes log entries, grouping the log entries into clusters of log entry types based on number of occurrences and average time interval, and discovering a sequence of the log entry types within each of the clusters. The sequence of the log entry types is based on a shortest path from a first one of the log entry types to a last one of the log entry types.
Apparatus with temperature mitigation mechanism and methods for operating the same
Methods, apparatuses, and systems related to a memory device are described. A controller may be configured to predict a temperature of a memory based on a real-time temperature of the controller. Based on the predicted temperature of the memory, the controller may execute a remedial action to reduce an actual temperature of the memory for executing an upcoming operation.