G06F11/0754

Inline flash memory qualification in a storage system

Reading data stored at a free block of a storage device is read prior to allocating the free block for storage of data. A determination as to whether a number of bit flips of the data stored at the free block is below a threshold is made. The free block is added to a pool of active free blocks to be allocated for the storage of data upon determining that the number of bit flips of the data stored at the free block is below the threshold.

Detecting out-of-bounds violations in a hardware design using formal verification

A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.

Systems and methods for software and developer management and evaluation
11662997 · 2023-05-30 · ·

A method of calculating a failure probability of a change in one or more source code repositories comprises analyzing at least one commit made to the source code repositories, determining a type of the commit selected from a fixing commit and a new code commit, if the commit is a new code commit, determining a set of areas of source code modified, if the code is a fixing commit, determining which commit of a plurality of new code commits is the causing commit, analyzing the commit message and calculating one or more parameters of the commit message, training a machine learning classifier with the set of data, and using the machine learning classifier to calculate a probability that the commit will cause a failure in the source code repository. Methods and systems for task assignment and test selection are also described.

Memory device on-die ECC data

Methods, devices, and systems related to memory device on-die ECC data are described. In an example, a scrub operation can be performed on data in order to determine which rows of memory cells in an array include a particular number of errors. The particular number of errors can be a number of errors that exceed a threshold number of errors. An address of the determined rows with the particular number of errors can be stored in memory cells of the array for later access. The address of the determined rows can be accessed to perform a user-initiated repair operation, a self-repair operation, a refresh operation, and/or to alter timing of access of the cells or alter voltage of the cells.

STACK PIVOT EXPLOIT DETECTION AND MITIGATION
20230160860 · 2023-05-25 ·

Examples of the present disclosure describe systems and methods for detecting and mitigating stack pivoting exploits. In aspects, various “checkpoints” may be identified in software code. At each checkpoint, the current stack pointer, stack base, and stack limit for each mode of execution may be obtained. The current stack pointer for each mode of execution may be evaluated to determine whether the stack pointer falls within a stack range between the stack base and the stack limit of the respective mode of execution. When the stack pointer is determined to be outside of the expected stack range, a stack pivot exploit is detected and one or more remedial actions may be automatically performed.

SYSTEMS AND METHODS FOR DATA-DRIVEN PROACTIVE DETECTION AND REMEDIATION OF ERRORS ON ENDPOINT COMPUTING SYSTEMS

Systems and methods for proactive support of computing assets are presented. In contrast to existing techniques of reactive support, the proactive support techniques disclosed herein automatically collect operating data from a plurality of computing devices, analyze the operating data to identify predictive indicators associated with error conditions, identify a subset of affected computing devices that match the predictive indicators, and execute corrective scripts to remediate or avoid such error conditions before problems are experienced on the affected computing devices. The operating data may be used to train a machine learning model in order to identify the predictive indicators associated with each error condition. In some embodiments, the corrective scripts may be automatically generated to adjust operating parameters or applications of the affected computing devices based upon the identified predictive indicators.

Identification and remediation of memory leaks using rule-based detection of anomalous memory usage patterns
11630754 · 2023-04-18 · ·

An apparatus comprises a processing device configured to initiate, in response to a designated event, monitoring of memory allocation and de-allocation operations associated with a given application, to maintain a memory allocation operation data structure comprising entries each corresponding to a memory allocation operation not having an associated memory de-allocation operation, and to determine whether memory usage of the given application corresponds to any of a set of anomalous memory usage pattern rules based on the memory allocation operation data structure. The processing device is also configured to identify the given application as being a cause of a memory leak responsive to determining that the memory usage of the given application corresponds to one or more of the anomalous memory usage pattern rules, and to perform remedial action for preventing or resolving the memory leak responsive to identifying the given application as being the cause of the memory leak.

DATA LOGGER FOR PROCESSING LOGISTICS-RELATED INFORMATION AND COLD CONTAINER INCLUDING THE SAME

Provided is a data logger. A data logger includes a sensor configured to sense a change in a gravitational acceleration of the data logger and a change in a rotation angle of the data logger, and generate a sensing signal, a communication module configured to receive configuration information including a sensing period and threshold values of the data logger from a portable reader, and a microprocessor unit configured to receive the sensing signal from the sensor, receive the sensing period and the threshold values from the communication module, generate sensing values corresponding to the sensing signal, compare the sensing values with the threshold values, determine whether an abnormal state occurs in the data logger according to a result of the comparison, generate and transmit to a server normal log information at each of the sensing period when the abnormal state does not occur in the data logger, and generate and transmit to the server abnormal log information whenever the abnormal state occurs regardless of the sensing period.

METHODS FOR RESTRICTING READ ACCESS TO SUPPLY CHIPS
20230069877 · 2023-03-09 ·

An example method for restricting read access to content in the component circuitry and securing data in the supply item is disclosed. The method identifies the status of a read command, and depending upon whether the status disabled or enabled, either blocks the accessing of encrypted data stored in the supply chip, or allows the accessing of the encrypted data stored in the supply chip.

STATE-BY-STATE PROGRAM LOOP DELTA DETECTION MODE FOR DETECTING A DEFECTIVE MEMORY ARRAY

Apparatuses and techniques are described for detecting a defect in a memory cell array during program operations. A defect can be detected by comparing the programming speed of memory cells connected to different word lines, for one or more programmed data states. The comparison can involve adjacent word lines in a block, or word lines in different blocks and planes. The comparison involves comparing two word lines in terms of a number of program-verify loops used to reach the programmed data states or to transition between programmed data states. If a program loop delta is not within an allowable range for one or more of the programmed data states, it can be concluded that a defect is present. The block which has the slower programming word line can be identified as a bad block.