In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.

The automatic troubleshooting of failed single sign on attempts via an identity provider to a service provider. When an error message is encountered due to that failed single sign on attempt, that error message is used to automatically identify a root cause of the failure of the single sign on attempt. In some embodiments, a resolution of the failure is also identified, and a tool for the resolution automatically provided to the user. Such failures in single sign on attempts usually are due to improper configuration information being provided to the identity provider. The principles described herein allow a user to test ahead of time whether they have provided proper configuration information to the identity provider, and potentially correct any problems in the single sign on experience in advance, perhaps well in advance of actually needing a resource provided by the service provider.

In an embodiment, a system and method for supporting a seeding process with suspend and resume capabilities are described. A resumable seeding component in a data seeding module can be used to move data from a source tier to a target tier. A resumption context including a perfect hash function (PHF) and a perfect hash vector (PHV) persists a state of a seeding process at the end of each operation in the seeding process. The PHV represents data segments of the data using the PHF. The resumption context is loaded into memory upon resumption of the seeding process after it is suspended. Information in the resumable context is used to determine a last successfully completed operation, and a last copied container. The seeding process is resumed by executing an operation following the completed operation in the resumable context.

Identifying computer program execution characteristics for determine relevance of pattern instruction executions to determine characteristics of a computer program. Filters are utilized to determine which subsequent occurrences of execution of at least one computer instruction are relevant to a counter based on execution characteristics of the at least one computer instruction where the counter counts the subsequent occurrences of execution of at least one computer instruction following prior executions of the same at least one computer instruction.

Methods, apparatus, systems and articles of manufacture are disclosed for safety mechanisms to actively detect address faults. An example system includes a first parity generator, a second parity generator, and a parity checker. The first parity generator is to generate a first parity based on a first address information. The first address information corresponds to a desired location to store data in a memory storage array. The second parity generator is to generate a second parity based on a second address information. The second address information corresponding to an actual location where the data is stored in the memory storage array. The parity checker is to compare the first parity and the second parity to detect a fault.

Embodiments are disclosed for problematic characters. The techniques include configuring a sort utility of an operating system to generate a replacement file that resolves a problem of a problematic file. Configuring the sort utility includes identifying the problematic file. The techniques further include identifying the replacement file. Additionally, configuring the sort utility includes providing an input to the sort utility that specifies a problematic character and a replacement character. Also, configuring the sort utility includes generating the replacement file by executing the configured sort utility.

A signal processing circuit has: n+1 (n being an integer of 2 or greater) operation circuits, each of which is configured to execute a prescribed operation process on inputted data; a signal supply unit that is configured to receive n pieces of input data extracted from one input signal and receive test data inputted separately from the n pieces of input data, sequentially select one operation circuit among the n+1 operation circuits and supply the test data to the one selected operation circuit, and supply the n pieces of input data to n operation circuits other than the one operation circuit among the n+1 operation circuits; and an anomaly determination unit that is configured to determine whether an anomaly has occurred in the one operation circuit on the basis of an operation result of an operation on the test data by the one operation circuit.

An electronic circuit includes a data bus, a first module, and a second module. The first module is coupled to the data bus and corresponds to a first address. The first module performs a first function and includes a first storage location for first configuration data for the first function and first error checking data. The first module also includes a first local configuration checker having a first identification code. The first error checking data is based on the first configuration data and the first identification code. The second module is coupled to the data bus and corresponds to a second address. The second module performs a second function and includes a second storage location for second configuration data and second error checking data. The second module also includes a second local configuration checker having a second identification code that is distinct from the first identifica

A controller controls a control target device and includes: a storage unit to record event history data of an event occurring during operation of the controller; a hash value calculation unit to calculate a hash value on the basis of the event history data; and a communication unit to transmit the hash value to another controller external to the controller.

Various techniques provide systems and methods for facilitating truly random bit generation. In one example, a method includes receiving a first truly random bit stream in a first memory that includes a plurality of memory cells. Each of the plurality of memory cells stores a respective one bit of the first truly random bit stream. The method further includes generating, by a logic circuit, each bit of a second truly random bit stream based on a respective pair of bits of the first truly random bit stream. The method further includes storing the second truly random bit stream in a second memory. Related methods and devices are also provided.