An electronic circuit includes a data bus, a first module, and a second module. The first module is coupled to the data bus and corresponds to a first address. The first module performs a first function and includes a first storage location for first configuration data for the first function and first error checking data. The first module also includes a first local configuration checker having a first identification code. The first error checking data is based on the first configuration data and the first identification code. The second module is coupled to the data bus and corresponds to a second address. The second module performs a second function and includes a second storage location for second configuration data and second error checking data. The second module also includes a second local configuration checker having a second identification code that is distinct from the first identification code.

An electronic circuit includes a data bus, a first module, and a second module. The first module is coupled to the data bus and corresponds to a first address. The first module performs a first function and includes a first storage location for first configuration data for the first function and first error checking data. The first module also includes a first local configuration checker having a first identification code. The first error checking data is based on the first configuration data and the first identification code. The second module is coupled to the data bus and corresponds to a second address. The second module performs a second function and includes a second storage location for second configuration data and second error checking data. The second module also includes a second local configuration checker having a second identification code that is distinct from the first identification code.

A security integrated circuit (IC) includes a memory including a first register and a second register, a token generation circuit configured to generate first data based on first bits of interest extracted before performance of an operation by using the first register, generate a first token by converting the first data, generate second data based on second bits of interest extracted after the performance of the operation by using the second register, and generate a second token by converting the second data, and an error detection circuit configured to detect an error on the first and second bits of interest by comparing the first token with the second token.

The present invention provides a control method of a server, wherein the control method includes the steps of: periodically controlling a first register and a second register of a first node to have a first value and a second value, respectively; periodically controlling a third register and a fourth register of a second node to have a third value and a fourth value, respectively; controlling the first register and the fourth register to synchronize with each other, wherein the first value is different from the fourth value; controlling the second register and the third register to synchronize with each other, wherein the second value is different from the third value; and periodically checking if the third register has the third value and the fourth register has the fourth value to determine if the first node fails to work.

A computing device receives an input that corresponds to a first part of a multi-part operation performed by an application executing on the computing device. In response to receiving the input corresponding to the first part of the multi-part operation, the computing device initiates an ongoing haptic output sequence. After initiating the ongoing haptic output sequence, the computing device receives an input that corresponds to a second part of the multi-part operation. In response to receiving the input corresponding to the second part of the multi-part operation, the computing device terminates the ongoing haptic output sequence.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for implementing a zero knowledge prover are disclosed. In one aspect, a method includes the actions of accessing an instruction set of a processor. The actions include generating a representation of a computing instruction using Boolean logic operations. The actions include assigning a polynomial constraint of a group of polynomial constraints to each Boolean logic operation. The actions include providing, to the processor, an executable program that includes various computing instructions and a request to execute the executable program. The actions include monitoring a value of a register of the processor. The actions include determining whether the value of the register complies with polynomial constraints of the group of polynomial constraints that correspond to instructions performed on the register. The actions include determining whether the execution of the executable program by the processor has been interfered with.

A method performed by a controller of a solid state drive (SSD) comprising receiving from a host a write request to store write data in a nonvolatile semiconductor storage device of the SSD. The method also comprises identifying a first codeword and a second codeword stored in the nonvolatile storage device, the first codeword and the second codeword configured to store write data corresponding to the write request. Responsive to the write request, the method comprises writing a first portion of the write data to the first codeword and writing a second portion of the write data to the second codeword, and sending a message to the host once the write data has been written to the nonvolatile semiconductor storage device. The first and second codewords are adjacently stored, and the write data has a length that is greater than the length of the first and second codewords.

The present disclosure discloses a timing index anomaly detection method, device and apparatus. The method includes the following operations. A plurality of pieces of timing index information about a service to be detected is acquired. The plurality of pieces of timing index information is filtered according to a filtering condition, and timing index information satisfying a preset filtering condition is retained. The filtering condition corresponds to an anomaly detection condition. A tag is added to the timing index information satisfying the preset filtering condition to form first timing index information. The tag is used for identifying the anomaly detection condition. The first timing index information is forwarded to a preset working node corresponding to the tag. anomaly detection is performed on the first timing index information on the same preset working node. It is determined whether an anomaly prompt is output.

Embodiments of information handling systems (IHSs) and computer-implemented methods are provided herein for testing system memory (or another volatile memory component) of an IHS. In the disclosed embodiments, memory testing is performed automatically: (a) during the pre-boot phase each time a new page of memory is allocated for the first time after a system boot, and (b) during OS runtime each time a read command is received and/or an event is detected. By proactively testing each page of memory, as the page is allocated but before information is stored therein, the systems and methods disclosed herein prevent “bad” memory pages from being used.

A system for detecting a disruption in a communication system of a vehicle. The system includes a vehicle bus and an electronic processor. The electronic processor is configured to receive a message, from a vehicle bus. The message has a format and a plurality of signals. The electronic processor is configured to detect anomalies in a bus identifier, the message format, a time the message is received, and a signal parameter of a signal of the plurality of signals. The electronic processor is also configured to generate an error if an anomaly is detected in the message format, an anomaly is detected in the time the message is received, or an anomaly is detected in the signal parameter of the signal of the plurality of signals.