Patent classifications
G06F11/0775
Adjusting a data storage address mapping in a maintenance free storage container
A method includes sending, by a computing device, an access request to one or more site controllers. The method further includes identifying, by a site controller, storage containers based on DSN addresses. The method includes sending, by the site controller, the access request to the identified storage containers. The method includes interpreting, by a container controller, the access request to identify storage units affiliated with some of the DSN addresses. The method includes determining, by the container controller, whether the storage units are in a storage failure mode. The method includes when the storage units are in the storage failure mode, determining, by the container controller, whether to rebuild, to change virtual to physical address mapping, or to migrate encoded data slices. The method includes, when the encoded data slices are to be rebuild, facilitating, by the container controller, rebuilding of the encoded data slices.
Management and correlation of network identification for communication errors
Various embodiments for management and correlation of communication errors by a processor device. A log is maintained that records each assignment of a particular network identification (ID) with a specific device in a computer storage network, including at least one of a date the ID was assigned and a time the ID was assigned, such that a trace or review may later be performed to correlate the specific device with data associated with the device at the at least one of the date and the time for troubleshooting purposes.
Enabling symptom verification
Systems, products and methods for enabling symptom verification. Verifying a symptom may include eliminating repeated symptom definitions or eliminating symptoms having low accuracy. A computer system enables verification of a symptom including a rule for detecting a set of events related to a given problem. The computer system includes a symptom database which stores the symptom, a specimen database which stores a specimen including a set of events detected according to a rule of a certain symptom, and an analysis unit which analyzes the specimen stored in the specimen database using a new symptom in order to determine whether to add the new symptom to the symptom database. The present disclosure also includes a method and a computer program for enabling verification of a symptom including a rule for detecting a set of events related to a given problem.
ERROR DETECTION AND MITIGATION FOR SOFTWARE PULL REQUESTS
Among other things, embodiments of the present disclosure relate to detecting and mitigating errors associated with software pull requests (PRs). Other embodiments may be described or claimed.
BUSINESS LANGUAGE PROCESSING USING LoQoS AND rb-LSTM
Provided is a language processing system and method for training a machine learning model to match two sets of text content such as incidents and solutions. In one example, the method may include storing a plurality of incident-solution pairs, generating latent scoring values for the plurality of incident-solution pairs based on latent features identified within the plurality of incident-solution pairs, building a data structure with incident-solution data from the plurality of incident-solution pairs stored therein, where each row in the data structure corresponds to a different incident-solution pair, and the data structure comprises one or more of a column for incident data, a column for solution data, and a column for latent scoring values, and inputting the data structure into a machine learning model to train the machine learning model to identify solutions from incidents.
Memory system and operating method thereof
A memory system includes a status information register configured for checking threshold voltages of select transistors included in memory blocks, storing status information on a check result, and outputting a code based on the status information, a status monitor configured to receive the code from the status information register, determine a number of select transistors that have shifted according to the code, and output status signal based on the number of the select transistors that have shifted, and a central processing unit configured for outputting a setup command set for setting parameters of the memory blocks, outputting a re-program command set for re-programming the select transistors, or outputting a bad block address for processing the memory blocks as bad blocks in response to the status signals.
STORAGE DEVICE HAVING VARIOUS RECOVERY METHODS AND RECOVERY MODES
A storage device including: a nonvolatile memory device including a plurality of nonvolatile memory cells, a partial storage area and an overprovision storage area; and a controller configured to control the nonvolatile memory device, wherein when the controller detects a fault of the nonvolatile memory device, the controller negates the partial storage area, reassigns the overprovision storage area, which corresponds to a size of a user area, among the partial storage area, determines a device fail if the overprovision storage area is less than an overprovision threshold after the reassigning of the partial storage area, and determines a recovery success if the overprovision storage area is equal to or greater than the overprovision threshold after the reassigning of the partial storage area.
Utilizing locally decodable redundancy data in a vast storage network
A network storage system operates by: sending, to at least one storage unit of a storage network, at least one read request corresponding to at least a read threshold number of a set of encoded data slices to be retrieved, wherein the set of encoded data slices correspond to a data segment, wherein the data segment is codable in accordance with dispersed error coding parameters that include a write threshold number and the read threshold number, wherein the write threshold number is a number of encoded data slices in the set of encoded data slices and wherein the read threshold number is a number of the set of slices that is required to decode the data segment; receiving from the at least one storage unit, a first subset of encoded data slices of the set of encoded data slices, wherein the first subset of encoded data slices is missing at least one missing encoded data slice from the number of the set of slices that is required to decode the data segment and that was not received from the at least one storage unit in response to the at least one read request; generating at least one rebuilt encoded data slice corresponding to the at least one missing encoded data slice utilizing locally decodable redundancy data, wherein the locally decodable redundancy data includes a plurality of local redundancy slices generated from a second subset of the set of encoded data slices that includes the at least one missing encoded data slice; and recovering the data segment based on the at least one rebuilt encoded data slice and the first subset of encoded data slices.
Supporting fault information delivery
A processor implementing techniques to supporting fault information delivery is disclosed. In one embodiment, the processor includes a memory controller unit to access an enclave page cache (EPC) and a processor core coupled to the memory controller unit. The processor core to detect a fault associated with accessing the EPC and generate an error code associated with the fault. The error code reflects an EPC-related fault cause. The processor core is further to encode the error code into a data structure associated with the processor core. The data structure is for monitoring a hardware state related to the processor core.
SELF-TESTING IN A PROCESSOR CORE
Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. Separate self-test control circuitry causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a second state of executing a self-test sequence of instructions, before returning to the first state of executing the data processing instructions without a reboot of the processor core circuitry being required. There is also self-test support circuitry, wherein the processor core circuitry is responsive to the self-test sequence of instructions to cause an export of at least one self-test data item via the self-test support circuitry to the self-test control circuitry.