According to one embodiment, a memory system includes first and second memory cells and a controller. The controller obtains first and second data based on a first read operation from the first and second memory cells, respectively. The controller obtains third and fourth data based on a second read from the first and second memory cells, respectively. The second read operation is different from the first read operation in a read voltage. The controller sets first and second values indicating likelihood of data stored in the first and second memory cells, respectively, based on information indicating locations of the first and second memory cells. The controller performs error correction on data read from the first and second memory cells using at least the third data and the first value, and using at least fourth data and the second value, respectively.

A semiconductor system includes a process control circuit configured to determine whether to perform a patrol training operation, generate a voltage code signal for adjusting a level of a reference voltage which determines a logic level of data in a target memory circuit, and adjust the voltage code signal on the basis of a fail information signal corresponding to the target memory circuit, an operation control circuit configured to receive a command and an address from a host, generate, from the command, a write signal and a read signal for performing a normal operation, and generate, from the address, an internal address for performing the normal operation and an error detection circuit configured to detect an error in the data by receiving the data from the target memory circuit, and generate the fail information signal depending on whether the error has occurred in the data.

An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.

The present disclosure provides methods, systems, and non-transitory computer readable media for performing data transfers with improved error encoding. The methods include receiving a request for data transfer from a source medium in the data storage system to a destination medium in the data storage system, wherein the data storage system comprises a computer cluster and a storage cluster; determining whether the source medium and the destination medium are within the storage cluster; based on the determination of whether the source medium and the destination medium are within the storage cluster, transferring the data from the source medium to the destination medium, wherein: the data is transferred without performing error correcting code check when the data is transferred within the storage cluster, and the data is transferred with an error correcting code check when the data is transferred between the computer cluster and the storage cluster.

Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, when updating a target firmware, a memory system may receive, from a host, a temporary firmware for increasing the size of a buffer from a preset first size to a second size equal to or greater than the size of the target firmware, may load and execute the temporary firmware into a processor, may receive the target firmware from the host and write the target firmware to the buffer, and may write the target firmware to the memory device.

A method for exchange of equipment performance data includes the steps of: obtaining performance data of a communicatively-insulated device; converting the performance data into a scannable code; capturing an image of the scannable code; decoding the scannable code using a communicatively-enabled device to extract an address string encoded in the scannable code, the address string comprising an address of a remote server and the performance data; initiating, by the communicatively-enabled device, a communications link with the remote server using the address string thereby to provide the performance data to the remote server; performing, by the remote server, analytics on the performance data; and sending historic device performance data and/or analytical results to a remote computing device and/or sending a link to the historic device performance data and/or analytical results to the remote computing device; wherein the communicatively-insulated device is packaging equipment and wherein obtaining the performance data comprises: running a calibration phantom through the packaging equipment; scanning the calibration phantom with a calibration unit; and using the calibration unit to generate a system status report identifying one or more operational parameters of the packaging equipment.

An integrated circuit (IC) includes: a storage having a storage interface and addressable bytes, the storage interface coupled to first and second sets of peripheral terminals; control circuitry having control circuitry inputs and control circuitry outputs, the control circuitry inputs coupled to the storage interface and configured to receive configuration bits provided by the storage responsive to a control circuitry update trigger, and the control circuitry outputs coupled to first and second sets of peripheral outputs; and a cyclic-redundancy check (CRC) engine coupled to the storage interface, the CRC engine configured to distinguish between purposeful updates to the data in the storage and bit errors in the data in the storage.

According to an embodiment, when a storage status of a first storage unit is recognized as a protected state, a control unit writes data to a second storage unit. When a read target address is recorded in a data migration log area, the control unit reads data from the second storage unit. When the read target address is not recorded in the data migration log area, the control unit reads data from the first storage unit.

Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

A device includes an interface configured to connect to a communication link. A controller of the device is configured to generate a redundancy code using first data and second data, and to transmit the redundancy code together with the first data to the interface.