Techniques described herein relate to systems and methods of data storage, and more particularly to providing layering of file system functionality on an object interface. In certain embodiments, file system functionality may be layered on cloud object interfaces to provide cloud-based storage while allowing for functionality expected from a legacy applications. For instance, POSIX interfaces and semantics may be layered on cloud-based storage, while providing access to data in a manner consistent with file-based access with data organization in name hierarchies. Various embodiments also may provide for memory mapping of data so that memory map changes are reflected in persistent storage while ensuring consistency between memory map changes and writes. For example, by transforming a ZFS file system disk-based storage into ZFS cloud-based storage, the ZFS file system gains the elastic nature of cloud storage.

Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system identifies, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system generates one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system then corrects the set of bits based on the candidate set of bits identified as error-free.

Systems, apparatuses, and methods related to modified checksum data using a poison data indictor. An example method can include receiving a first set of bits including data and a second set of at least one bit indicating whether the first set of bits includes one or more erroneous or corrupted bits. A first checksum can be generated that is associated with the first set of bits. A second checksum can be generated using the first checksum and the second set of at least one bit. The first set of bits and the second checksum can be written to an array of a memory device. A comparison of the first checksum and the second checksum can indicate whether the first set of bits includes the at least one or more erroneous or corrupted bits.

The present disclosure relates to a chip booting control method, a chip, a display panel, and an electronic apparatus. The method is applied to a control circuit of a chip, and the chip further includes a buffer. The method includes: reading first booting information from the buffer in response to a chip triggering non-power-down reset, the first booting information being used to boot the chip; determining whether the first booting information satisfies a first preset condition; and booting the chip according to the first booting information in response to the first booting information satisfying the first preset condition.

A hardware neural network engine which uses checksums of the matrices used to perform the neural network computations. For fault correction, expected checksums are compared with checksums computed from the matrix developed from the matrix operation. The expected checksums are developed from the prior stage of the matrix operations or from the prior stage of the matrix operations combined with the input matrices to a matrix operation. This use of checksums allows reading of the matrices from memory, the dot product of the matrices and the accumulation of the matrices to be fault corrected without triplication of the matrix operation hardware and extensive use of error correcting codes. The nonlinear stage of the neural network computation is done using triplicated nonlinear computational logic. Fault detection is done in a similar manner, with fewer checksums needed and correction logic removed as compared to the fault correction operation.

Data is accessed from a particular register first device that is connected to a second device via a link that includes at least one retimer device. The particular register corresponds to requests to be sent in in-band transactions with the retimer, and the data corresponds to a particular transaction with the retimer. At least one ordered set is generated at the first device to comprise a subset of bits encoded with the data, where the ordered set with the encoded subset of bits is to be sent on the link and the subset of bits are to be processed by the retimer in the particular transaction.

A method and a device of cyclic redundancy check are provided. The method includes determining a payload portion, the payload portion including at least one information field for carrying information bits; determining input bits for generating CRC bits, the input bits including information bits carried in a part or all of at least one information field; generating target CRC bits according to the input bits; generating control information including the payload portion and the target CRC bits.

A method includes: storing a first data extent on a physical medium, wherein the physical medium is divided into a plurality of storage blocks, wherein each of the storage blocks has a size that is different than a size of the first data extent, further wherein the first data extent is stored to a first block of the plurality of storage blocks; generating a descriptor for the first data extent, wherein the descriptor indicates that the first data extent starts within the first block of the plurality of blocks and indicates an offset from the beginning of the first block at which the first data extent starts; and storing the descriptor within the first block.

A memory system and a memory controller are disclosed. By determining whether an error has occurred in target data stored in a predetermined target memory area of the memory device and determining, in response to whether an error has occurred in the target data, the magnitude of the supplied power based on a first operation parameter selected among predetermined candidate operation parameters in connection with the magnitude of the supplied power, the memory controller may stably drive a firmware, and may handle an operation error of the firmware due to a change in external environment.

A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.