A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

The technology disclosed in this patent document can be implemented in embodiments to provide a memory system capable of improving a read operation, using an error correction technique (e.g., chipkill) that recovers data in correcting a data failure including a multibit failure, and an operation method of the memory system. The disclosed read operations based on recovery can be used for retrieving data from a memory chip by reconstructing the same data from other memory chips without accessing the memory chip and can be applied in various memory systems.

Disclosed are techniques for managing parity information for data stored on a storage device. A method can be implemented at a computing device communicably coupled to the storage device, and include (1) receiving a request to write data into a data band of the storage device, (2) writing the data into stripes of the data band, comprising, for each stripe of the data band: (i) calculating first parity information for the data written into the stripe, (ii) writing the first parity information into a volatile memory, and (iii) in response to determining that a threshold number of stripes have been written: converting the first parity information into smaller second parity information, and (3) in response to determining that the data band is read-verified: (i) converting the second parity information into smaller third parity information, and (ii) storing the smaller third parity information into a parity band of the storage device.

A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

The present disclosure includes apparatuses and methods related to data movement operations in non-volatile memory. An example apparatus can comprise an array of non-volatile memory cells including a plurality of sections each with a plurality of rows and a controller configured to move data stored in a first portion of the array from a first row of a first section to a second row of the first section and move data stored in a second portion of the array from a second section to the first to create an open row in the second section in response to data from a particular number of portions of memory cells in the first section being moved within the first section.

An embodiment includes a method for use in operating a memory chip, the method comprising: operating the memory chip with an increased burst length relative to a standard burst length of the memory chip; and using the increased burst length to access metadata during a given operation of the memory chip. Another embodiment includes a memory module, comprising a plurality of memory chips, each memory chip being operable with an increased burst length relative to a standard burst length of the memory chip, the increased burst length being used to access metadata during a given operation of the memory module.

A read method executed by a computing system includes a processor, at least one nonvolatile memory, and at least one cache memory performing a cache function of the at least one nonvolatile memory. The method includes receiving a read request regarding a critical word from the processor. A determination is made whether a cache miss is generated, through a tag determination operation corresponding to the read request. Page data corresponding to the read request is received from the at least one nonvolatile memory in a wraparound scheme when a result of the tag determination operation indicates that the cache miss is generated. The critical word is output to the processor when the critical word of the page data is received.

Disclosed are techniques for managing context information for data stored within a computing device. According to some embodiments, the method can include the steps of (1) loading, into a volatile memory of the computing device, the context information from a non-volatile memory of the computing device, where the context information is separated into a plurality of portions, and each portion of the plurality of portions is separated into a plurality of sub-portions, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: identifying a next sub-portion to be processed, where the next sub-portion is included in the plurality of sub-portions of a current portion being processed, identifying a portion of the context information that corresponds to the next sub-portion, converting the portion from a first format to a second format, and writing the portion into the non-volatile memory.

A method is proposed for operating a controller of a solid state storage device. The method comprises encoding information and frozen bits with a polar code thereby obtaining polar encoded bits, storing the polar encoded bits in memory cells of the solid state storage device, reading the polar encoded bits stored in the memory cells of the solid state storage device, wherein the read polar encoded bits include the frozen bits and unfrozen bits indicative of said information bits, and performing a successive cancellation list (SCL) decoding of the read polar encoded bits. The step of performing a SCL decoding comprises: providing a list of candidate decoding paths; duplicating the candidate decoding paths included in the list of candidate decoding paths thereby obtaining duplicated candidate decoding paths; determining a reliability of the unfrozen bits included in the duplicated candidate decoding paths; determining a maximum list size indicative of an allowed maximum number of candidate decoding paths that can be contained in the list of candidate decoding paths based on a number of unfrozen bits included in the duplicated candidate decoding paths having a reliability below a predetermined threshold reliability; pruning at least one duplicated candidate decoding path among the duplicated candidate decoding paths according to the determined maximum list size and updating the list of candidate decoding paths by including in the list of candidate decoding paths a number of non-pruned duplicated candidate decoding paths not higher than the maximum list size; and selecting a decoding path from the list of candidate decoding paths thereby obtaining the information bits.

A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.