Disclosed is an interface control circuit including an error detection unit, an error correction unit, and an adjustment control unit. The error detection unit is configured to detect whether an error occurs in error correction coded data transmitted via an interface. The error correction unit is configured to execute error correction processing of correcting the error when the error occurs. The adjustment control unit is configured to start adjustment processing of adjusting a transmission characteristic of the interface when the error occurs.

In response to a first memory access transaction having a first base address, data fields and a repair fields are retrieved from a first DRAM channel. The data fields include a first data field. The repair fields include a first repair field storing repair data. The repair data is to replace any data in the first data field. In response to a second memory access transaction having a second base address, repair tag fields are retrieved from a second DRAM channel. The repair tag fields include a repair tag field that indicates the repair data is be replace the data stored in the first data field.

A method of failure detection in a storage system is performed by the storage system. The method includes detecting a failure in a nonvolatile random access memory device that is in or coupled to a storage device having storage memory. The storage system has multiple NVRAM devices and multiple storage devices that have storage memory. The method includes taking a portion or all of the NVRAM device offline. Taking a portion or all of the NVRAM device offline is responsive to detecting the failure. Taking a portion or all of the NVRAM device off-line is while keeping online the storage memory of the storage device, sufficient ones of the NVRAM devices, and sufficient ones of the storage devices to provide reliable access to data and metadata in the storage system.

A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system provides a one-hot address cache comprising a plurality of one-hot addresses and a host interface to a host memory controller of a host system. Each one-hot address of the plurality of one-hot addresses has a bit width. The plurality of one-hot addresses is configured to store the data associated with a corresponding memory address in an address space of a memory system and provide the data to the host memory controller during a memory map learning process. The plurality of one-hot addresses comprises a zero address of the bit width and a plurality of non-zero addresses of the bit width, and each one-hot address of the plurality of non-zero addresses of the one-hot address cache has only one non-zero address bit of the bit width.

According to one embodiment, a memory device includes a first address memory storing a first address; a controller which is based on a first interface which transmits a signal serially and outputs a first command in accordance with the first interface; and a memory which stores data in a nonvolatile manner, is based on the first interface, and stores received write data in an address based on the first address when the memory receives the first command.

A non-volatile storage system is provided that includes a mechanism to restore data that has been corrupted beyond the limits of traditional error correction. The system creates first level parity information for each subset of data to form multiple sets of programmable data, with each set of programmable data including a subset of data and corresponding first level parity. Separate second level parity is created for each set of programmable data. The system creates combined second level parity information based on a function of separate second level parity information for the multiple sets of programmable data. If a set of programmable data is found to be corrupt, the corrupt subset of data is recovered using the corrupt subset of data read from the non-volatile storage system, the corresponding first level parity read from the non-volatile storage system and the combined second level parity information.

A semiconductor memory apparatus may include an error check and correction circuit block configured to receive a plurality of cell data, and output error-checked data and error data discrimination signals after receiving an error check enable signal; and a data bus inversion circuit block configured to receive the plurality of cell data, and output the plurality of cell data by inverting or non-inverting the cell data after receiving a read data bus inversion enable signal, the error check enable signal and the error data discrimination signals.

A read method executed by a computing system includes a processor, at least one nonvolatile memory, and at least one cache memory performing a cache function of the at least one nonvolatile memory. The method includes receiving a read request regarding a critical word from the processor. A determination is made whether a cache miss is generated, through a tag determination operation corresponding to the read request. Page data corresponding to the read request is received from the at least one nonvolatile memory in a wraparound scheme when a result of the tag determination operation indicates that the cache miss is generated. The critical word is output to the processor when the critical word of the page data is received.

Some embodiments include apparatuses and methods having a memory structure included in a memory device and a control unit included in the memory device. The control unit can provide information obtained from the memory structure during a memory operation to a host device (e.g., a processor) in response to a command from the host device. If the control unit receives a notification from the host device indicating that the host device has detected an error in the information obtained from the memory structure, then a repair unit included in the memory device performs a memory repair operation to repair a portion in the memory structure.

Embodiments provide methodologies for reliably storing data within a storage system using liquid distributed storage control. Such liquid distributed storage control operates to compress repair bandwidth utilized within a storage system for data repair processing to the point of operating in a liquid regime. Liquid distributed storage control logic of embodiments may employ a lazy repair policy, repair bandwidth control, a large erasure code, and/or a repair queue. Embodiments of liquid distributed storage control logic may additionally or alternatively implement a data organization adapted to allow the repair policy to avoid handling large objects, instead streaming data into the storage nodes at a very fine granularity.