In a method for computer-assisted operation of a memory unit, encoded data is saved in the memory unit. The data is retrieved and decoded after retrieval. The memory unit is monitored for errors in that a temporal sequence of computer-assisted checking operations is carried out for the memory unit. For first-time encoding of the data, each required application data set is generated or selected, containing check data segments. For each application data set, the check data segment is occupied by count data, which characterizes the checking operation being implemented. After retrieving and decoding the application data sets, an error is determined when the count data characterizes neither the checking operation being implemented nor the most recent completely implemented checking operation. The check data segment of the relevant application data set is occupied by count data, which characterizes the checking operation being implemented, if no error was determined.

In a method for computer-assisted operation of a memory unit, data is saved in the memory unit and the data is encoded before saving, or data is retrieved from the memory unit and the data is decoded after retrieval. For first-time encoding of the data, at least one group of application data sets, containing data segments having identical application data for an application program and check data segments having different diversity characteristic data respectively, is generated or selected from a supply of possible diversity characteristic data. Each application data set is encoded and saved. The data is retrieved in that the application data sets are retrieved and decoded. Data is saved in that the application data sets are encoded and saved. Furthermore, a method for computer-assisted, repeated execution of an application program in redundant computing instances, a computer program product and a provision apparatus are disclosed.

A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBI.

Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

A processing system of a storage network operates by: receiving a write request to store a data object; selecting a selected memory type of a plurality of memory types to store the data object, based on object parameters associated with the data object; selecting a selected memory to store the data object, the selected memory having the selected memory type of the plurality of memory types; and facilitating storage of the data object in the selected memory having the selected memory type of the plurality of memory types, wherein the data object is dispersed error encoded and stored as a plurality of encoded data slices.

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

A method includes a computing device of a storage network obfuscating encoded data slices of a first set of encoded data slices of a plurality of sets of encoded data slices using an obfuscating method to produce obfuscated encoded data slices. The method further includes the computing device of the storage network outputting the obfuscated encoded data slices for storage in the storage network.

A system and method for adaptive RAID geometries. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to determine a first RAID layout for use in storing data, and write a first RAID stripe to the device group according to the first RAID layout. In response to detecting a first condition, the controller is configured to determine a second RAID layout which is different from the first RAID layout, and write a second RAID stripe to the device group according to the second layout, whereby the device group concurrently stores data according to both the first RAID layout and the second RAID layout.

A multi-core processor configured to improve processing performance in certain computing contexts is provided. The multi-core processor includes multiple processing cores that implement barrel threading to execute multiple instruction threads in parallel while ensuring that the effects of an idle instruction or thread upon the performance of the processor is minimized. The multiple cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate inter-cache coherency issues. The barrel-threading can minimize the latency impacts associated with a shared data cache. In some examples, the multi-core processor can also include a serial processor configured to execute single threaded programming code that may not yield satisfactory performance in a processing environment that employs barrel threading.