Patent classifications
G06F11/1076
Local data compaction for integrated memory assembly
An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die in response to commands from a memory controller. To utilize space more efficiently on the memory die, the control die compacts fragmented data on the memory die.
Method, device, and computer readable storage medium for managing redundant array of independent disks
Techniques manage a redundant array of independent disks. In such a technique, a response time of a first storage device in the RAID is compared to a first threshold. In response to the response time of the first storage device exceeding the first threshold, the first storage device is configured as a pseudo-degraded storage device, such that the pseudo-degraded storage device is responsive to write requests only.
Method and Storage System with a Non-Volatile Bad Block Read Cache Using Partial Blocks
A storage system has a memory with a multi-level cell (MLC) block and a partially-bad single-level cell (SLC) block. The storage system repurposes the partially-bad SLC block as a non-volatile read cache for data stored in the MLC block (e.g., cold data that is read relatively frequently) to improve performance of host reads. Because the original version of the data is still stored in the MLC block, the original version of the data can be read if there is an error in the copy of the data stored in the partially-bad SLC block, thus avoiding the need for extensive error-correction handling to account for the poor reliability of the partially-bad SLC block.
Protecting data memory in a signal processing system
Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.
Using erasure coding in a single region to reduce the likelihood of losing objects maintained in cloud object storage
Techniques for using erasure coding in a single region to reduce the likelihood of losing objects in a cloud object storage platform are provided. In one set of embodiments, a computer system can upload a plurality of data objects to a region of a cloud object storage platform, where the plurality of data objects including modifications to a data set. The computer system can further compute a parity object based on the plurality of data objects, where the parity object encodes parity information for the plurality of data objects. The computer system can then upload the parity object to the same region where the plurality of data objects was uploaded.
Method and system of deduplication of error codec in hyperscale infrastructure
The present disclosure provides methods, systems, and non-transitory computer readable media for performing data transfers with improved error encoding. The methods include receiving a request for data transfer from a source medium in the data storage system to a destination medium in the data storage system, wherein the data storage system comprises a computer cluster and a storage cluster; determining whether the source medium and the destination medium are within the storage cluster; based on the determination of whether the source medium and the destination medium are within the storage cluster, transferring the data from the source medium to the destination medium, wherein: the data is transferred without performing error correcting code check when the data is transferred within the storage cluster, and the data is transferred with an error correcting code check when the data is transferred between the computer cluster and the storage cluster.
MULTIPLE BLOCK ERROR CORRECTION IN AN INFORMATION HANDLING SYSTEM
An information handling system includes a first memory and a baseboard management controller. The first memory stores a first firmware partition and a second firmware partition. The baseboard management controller includes a second memory. The baseboard management controller begins execution of a DM-Verity daemon, and performs periodic patrol reads of the first firmware partition. The baseboard management controller detects one or more block failures in the first firmware partition, and stores information associated with the one or more block failures in a message box of the second memory. In response to the entire first firmware partition being scanned, the baseboard management controller switches a boot partition from the first firmware partition to the second firmware partition, and initiates a reboot of the information handling system.
Method for the secured storing of a data element in an external memory and interface module
A method for the secured storing of a data element in an external memory, which is connected to a microcontroller via an interface module, which is configured to calculate memory addresses for data to be stored and for error correction values. The method includes receiving the data element to be stored by the interface module, a calculation by the interface module of a memory address in the external memory for the data element to be stored, and a writing, starting at the memory address, of the data element and of the error correction value via the interface module into the external memory, the error correction value immediately following the data element being written and the writing taking place within one addressing phase. A corresponding interface module, a corresponding microcontroller, and a corresponding control unit are also described.
Identifying a parent event associated with child error states
Event records from multiple computing devices are received at a managing unit. Individual event records include an event identifier field including an event identifier identifying a first event associated with a particular computing device, a parent event identifier field identifying a parent event that initialized the first event, and an entity identifier field including an entity identifier identifying the particular computing device. The managing unit generates log records associated with event identifiers included in the event records. The log records include state fields indicating a state of a particular event associated with a particular event identifier. Based on a correlation of the event and log records, the managing unit determines at least two computing devices associated with events resulting in an error state, and identifies parent events that initialized the events with errors. The managing unit generates a report linking the parent events to the events having an error state.
Configuring new storage systems based on write endurance
A method performed by a computing device, of configuring a new design of a new data storage system (DSS) having initial configuration parameters is provided. The new design includes an initial plurality of storage drives. The method includes (a) collecting operational information from a plurality of remote DSSs in operation, the operational information including numbers of writes of various write sizes received by respective remote DSSs of the plurality of remote DSSs over time; (b) modeling a number of drive writes per day (DWPD) of the initial plurality of storage drives of the new DSS based on the collected operational information from the plurality of remote DSSs and the initial configuration parameters; (c) comparing the modeled number of DWPD to a threshold value; and (d) in response to the modeled number of DWPD exceeding the threshold value, reconfiguring the new DSS with an updated design.