Methods that can boot a target computing device and/or target computing system from a checkpoint image for the target computing device and/or target computing system generated at a source computing system are disclosed herein. One method includes generating, by a processor on a source computing system, a checkpoint image for a target computing device and distributing the checkpoint image from the source computing system to the target computing device. Here, the checkpoint image is stored in the host computing system and is configured to enable the target computing device to restore itself from the checkpoint image and the source computing system and the target computing device are separate computing entities. Apparatus, systems, and computer program products that can include, perform, and/or implement the methods are also disclosed herein.

A fault recoverable computer system including an instruction table having a plurality of processor instructions. The system also includes at least one sensor arranged to monitor an environmental condition and output sensor data. A monitor module is arranged to receive sensor data and/or processor state information. A testing module is arranged to perform a plurality of self-tests including a first self-test of the computer system and, if the first self-test fails, output a failure notification. A recovery module is arranged to update the instruction table in response to receiving the failure notification. The update includes replacing a first processor instruction arranged to perform a first function with a replacement set of processor instructions configured to alternatively perform the first function.

Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

A processing device performs a first process in a plurality of cycles to update a plurality of resources included in programmable resources. The processing device includes an instruction execution circuit that records that the first process is being executed, and makes an error notification when an error is detected during execution of an instruction, and a retry control circuit that records a type of the first process at a starting point of the first process, judges from the recorded type whether the first process is re-executable upon receiving the error notification during the first process, and instructs re-execution of the first process from a start of the first process in a case where the first process is judged to be re-executable. The instruction execution circuit performs a retry process to re-execute the first process when instructed from the retry control circuit to re-execute the first process.

A device for processing bit strings of a program flow including a data memory and an interface that is designed to output a second bit string, and a bit string manipulator that is designed to analyze the first bit string at a predetermined bit string section for information that indicates a target state of the program flow, and to manipulate the first bit string in the bit string section to obtain the second bit string.

An instruction storage circuit within a processor that includes an instruction memory and a memory control circuit. The instruction memory is configured to store instructions of a program for the processor. The memory control circuit is configured to receive a particular instruction from the instruction memory, detect a data integrity error in the particular instruction, and generate and store a corrected version of the particular instruction in an error storage circuit within the instruction memory. A flush of an execution pipeline may be performed in response to the error. In response to a refetch of the particular instruction after the pipeline flush, the instruction storage circuit may be configured to cause the particular instruction to be provided from the error storage circuit to the execution pipeline to permit forward progress of the processor.

An instruction storage circuit within a processor that includes an instruction memory and a memory control circuit. The instruction memory is configured to store instructions of a program for the processor. The memory control circuit is configured to receive a particular instruction from the instruction memory, detect a data integrity error in the particular instruction, and generate and store a corrected version of the particular instruction in an error storage circuit within the instruction memory. A flush of an execution pipeline may be performed in response to the error. In response to a refetch of the particular instruction after the pipeline flush, the instruction storage circuit may be configured to cause the particular instruction to be provided from the error storage circuit to the execution pipeline to permit forward progress of the processor.

Controlling access to an ERST, including: triggering, in response to an occurrence of an error, a SMI; adjusting, in response to the SMI and by a SMM RAS handler module, a slate of an access gate from a locked state to an unlocked state, the access gate controlling access to an ERST storage region; generating, by an OS MCE handler, an error record based on the error; accessing, by the OS MCE handler, an ACPI ERST to identify instructions for storing the error record at the ERST storage region; triggering, in response to the instructions and by the OS MCE handler, an additional SMI; determining, in response to the additional SMI and by a SMM handler, that the access gate is in the unlocked state; in response to determining that the access gate is in the unlocked state: storing, by the SMM handler, the error record at the ERST.

The invention discloses a method for controlling other systems based on a single-point execution contract, comprising the following steps: A, when a contract developer writes a single-point execution contract code, integrating a command needing transparent transmission into the code; B, executing, by a virtual machine, the code, calling a transparent-transmission channel command input interface while executing to a row with the command, and transmitting the command to a blockchain node; and C, not processing the command by the blockchain node, and calling a secondary development service package interface through the transparent-transmission command to transmit downwards. In the method, a command transparent-transmission channel and a transparent-transmission command secondary development package service are designed, so that a blockchain user can operate their specific software/hardware equipment through a user-defined command. The verification of the contract execution results is not influenced, and a situation where contract execution passed but verification failed can be avoided.

Replay of partially executed instruction blocks in a processor-based system employing a block-atomic execution model is disclosed. In one aspect, a partial replay controller is provided in a processor(s) of a central processing unit (CPU). If an instruction is detected in the instruction block associated with a potential architectural state modification, or an exception occurs during execution of instructions, the instruction block is re-executed. During re-execution of the instruction block, the partial replay controller is configured to record produced results from load/store instructions. Thus, if an exception occurs during re-execution of the instruction block, previously recorded produced results for the executed load/store instructions before the exception occurred are replayed during re-execution of the instruction block after the exception is resolved. Thus, execution of instructions leading up to side-effect operations in the instruction block can be deterministically repeated with previously produced results, without repeating the side-effects.