Patent classifications
G06F11/1415
Systems and methods for host image transfer
Methods and systems for transferring a host image of a first machine to a second machine, such as during disaster recovery or migration, are disclosed. In one example, a first profile of a first machine of a first type, such as a first client machine, is compared to a second profile of a second machine, such as a recovery machine or a second client machine of a second type different from the first type, to which the host image is to be transferred, by a first processing device. The first and second profiles each comprise at least one property of the first type of first machine and the second type of second machine, respectively. At least one property of a host image of the first machine is conformed to at least one corresponding property of the second machine. The conformed host image is provided to the second machine, via a network. The second machine is configured with at least one conformed property of the host image by a second processing device of the second machine.
METHOD FOR PLANNING RECOVERY RESOURCE FOR RESISTING N-TIME FAULTS AND OPTICAL TRANSMISSION DEVICE
The present application provides a method for planning a recovery resource for resisting N-time faults and an optical transmission device, and the method includes: planning, on an optical transmission device according to preset network planning information, a recovery resource for resisting (N−1)-time faults for preset (N−1)-time faults, and the recovery resource for resisting (N−1)-time faults is an optimal recovery resource corresponding to each interrupted service during the preset (N−1)-time faults; and planning, by the optical transmission device according to the network planning information and the recovery resource for resisting (N−1)-time faults, a recovery resource for resisting N-time faults for preset N-time faults, where the recovery resource for resisting N-time faults is a network-wide optimal recovery resource corresponding to interrupted services during the N-time faults. According to the present application, recovery resource costs can be reduced, and recovery resource planning reliability can be improved.
OPERATING SYSTEM RECOVERY ACTIONS
In an example implementation according to aspects of the present disclosure, a system comprising a processor and a memory. The memory comprises instructions that when executed cause the processor to receive a set of telemetry from client computing device. The processor applies a data model to the set of telemetry. The processor assigns a priority to an operating system recovery action based on the data modeling. The processor blocks the operating system recovery action based on the priority exceeding a first threshold.
Providing a Watchdog Timer to Enable Collection of Crash Data
A system and method for providing a watchdog timer to enable collection of crash data is provided. Upon execution of certain operations, a source thread of an application initiates a watchdog thread that periodically sample state of data relating to the application. Should the operation not complete within a watchdog timeout period, the watchdog thread invokes a crash function to collect additional state data. At least a portion of the state data is stored for later analysis and debugging.
SYSTEM AND METHOD FOR DATA BACKUP USING UNMANNED AERIAL VEHICLE (UAV)
Disclosed are systems, methods and computer program products for performing data backup using an unmanned aerial vehicle (UAV). An example method includes in response to detecting a data backup request from a user device, determining a geographic location of the user device and dispatching the UAV to the geographic location; controlling the UAV to obtain user data from the user device; and controlling the UAV to navigate to a data center to back up the obtained user data onto a cloud storage.
Runtime model validation for partially-observable hybrid systems
Disclosed herein are techniques to make the synthesized monitoring conditions of partially-observable hybrid systems robust to partial observability of sensor uncertainty and partial controllability due to actuator disturbance. The approach herein shows that the monitoring conditions result in provable safety guarantees with fallback controllers that react to monitor violation at runtime.
Memory system with low-latency read recovery and method of operating the memory system
Multiple memory systems with respective decoders employ a low latency implementation of a read recovery level feature in decoding data. The decoding comprises receiving from a host a read request for decoding read data at a first recovery level by a first memory system, a first decoder of the first memory system being set at a second recovery level with a corresponding maximum iteration number when the read request is received by the first memory system; and operating the first decoder, after a set time elapses, to decode the read data at the second recovery level. A second decoder of a second memory system is set at the first recovery level for at least part of the time during which the first decoder operates to decode the read data at the second recovery level.
Systems and methods for seamless redelivery of missing data
In some embodiments, apparatuses and methods are provided herein useful to providing seamless redelivery of missing data from a message broker to a requesting client computer. In some embodiments, there is provided a system for providing seamless redelivery of missing data including a requesting client computer generating a first data request in response to a user's e-commerce activity over an internet; a message broker comprising one or more first control circuits; a backup control circuit configured to copy a plurality of messages as a plurality of object data into an object store; and a reconciliation control circuit configured to: receive a second data request in response to a determination by the requesting client computer that a data loss has occurred; download the missing data from the object store; and provide the missing data to the message broker.
TECHNIQUES TO IMPROVE LATENCY OF RETRY FLOW IN MEMORY CONTROLLERS
A memory controller system includes error correction circuitry and erasure decoder circuitry. A retry flow is triggered when the memory controller's error checking and correction (ECC) detects an uncorrectable codeword. Error correction circuitry generates erasure codewords from the codeword with uncorrectable errors. The memory controller computes the syndrome weight of the erasure codewords. For example, the erasure decoder circuitry receives the erasure codewords and computes the syndrome weights. Error correction circuitry orders the erasure codewords based on their corresponding syndrome weights. Then error correction circuitry selects a subset of the codewords, and sends them to erasure decoder circuitry. Erasure decoder circuitry receives the selected codewords and decodes them.
Distributed erasure coded virtual file system
A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices comprises one or more of a plurality of storage devices. A plurality of failure resilient address spaces are distributed across the plurality of storage devices such that each of the plurality of failure resilient address spaces spans a plurality of the storage devices. Each one of the plurality of failure resilient address spaces is organized into a plurality of stripes. Each one or more stripes of the plurality of stripes is part of a respective one of a plurality of forward error correction (FEC) protection domains. Each of the plurality of stripes may comprise a plurality of storage blocks. Each block of a particular one of the plurality of stripes may reside on a different one of the plurality of storage devices.